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H83069RF Datasheet(PDF) 218 Page - Renesas Technology Corp |
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H83069RF Datasheet(HTML) 218 Page - Renesas Technology Corp |
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218 / 1003 page  Rev. 5.0, 09/04, page 196 of 978 7.1.2 Block Diagram Figure 7.1 shows a DMAC block diagram. IMIA0 IMIA1 IMIA2 ADI TXI0 RXI0 DREQ 0 DREQ 1 TEND 0 TEND 1 DEND0A DEND0B DEND1A DEND1B DTCR0A DTCR0B DTCR1A DTCR1B Control logic Data buffer Address buffer Arithmetic-logic unit MAR0A MAR0B MAR1A MAR1B IOAR0A IOAR0B IOAR1A IOAR1B ETCR0A ETCR0B ETCR1A ETCR1B Internal address bus Internal interrupts Interrupt signals Internal data bus [Legend] DTCR: MAR: IOAR: ETCR: Data transfer control register Memory address register I/O address register Execute transfer count register Channel 0A Channel 0B Channel 1A Channel 1B Channel 0 Channel 1 Figure 7.1 Block Diagram of DMAC |
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