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H83069RF Datasheet(PDF) 256 Page - Renesas Technology Corp

Part # H83069RF
Description  Renesas 16-Bit Single-Chip Microcomputer
PDF  1003 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H83069RF Datasheet(HTML) 256 Page - Renesas Technology Corp

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Rev. 5.0, 09/04, page 234 of 978
Activation by External Request: If an external request (
DREQ pin) is selected as an activation
source, the
DREQ pin becomes an input pin and the corresponding TEND pin becomes an output
pin, regardless of the port data direction register (DDR) settings. The
DREQ input can be level-
sensitive or edge-sensitive.
In short address mode and normal mode, an external request operates as follows. If edge sensing is
selected, one byte or word is transferred each time a high-to-low transition of the
DREQ input is
detected. If the next edge is input before the transfer is completed, the next transfer may not be
executed. If level sensing is selected, the transfer continues while
DREQ is low, until the transfer
is completed. The bus is released temporarily after each byte or word has been transferred,
however. If the
DREQ input goes high during a transfer, the transfer is suspended after the current
byte or word has been transferred. When
DREQ goes low, the request is held internally until one
byte or word has been transferred. The
TEND signal goes low during the last write cycle.
In block transfer mode, an external request operates as follows. Only edge-sensitive transfer
requests are possible in block transfer mode. Each time a high-to-low transition of the
DREQ
input is detected, a block of the specified size is transferred. The
TEND signal goes low during the
last write cycle in each block.
Activation by Auto-Request: The transfer starts as soon as enabled by register setup, and
continues until completed. Cycle-steal mode or burst mode can be selected.
In cycle-steal mode the DMAC releases the bus temporarily after transferring each byte or word.
Normally, DMAC cycles alternate with CPU cycles.
In burst mode the DMAC keeps the bus until the transfer is completed, unless there is a higher-
priority bus request. If there is a higher-priority bus request, the bus is released after the current
byte or word has been transferred.



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