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H83069RF Datasheet(PDF) 269 Page - Renesas Technology Corp |
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H83069RF Datasheet(HTML) 269 Page - Renesas Technology Corp |
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269 / 1003 page  Rev. 5.0, 09/04, page 247 of 978 7.5 Interrupts The DMAC generates only DMA-end interrupts. Table 7.13 lists the interrupts and their priority. Table 7.13 DMAC Interrupts Description Interrupt Short Address Mode Full Address Mode Interrupt Priority DEND0A End of transfer on channel 0A End of transfer on channel 0 High DEND0B End of transfer on channel 0B — DEND1A End of transfer on channel 1A End of transfer on channel 1 DEND1B End of transfer on channel 1B — Low Each interrupt is enabled or disabled by the DTIE bit in the corresponding data transfer control register (DTCR). Separate interrupt signals are sent to the interrupt controller. The interrupt priority order among channels is channel 0 > channel 1 and channel A > channel B. Figure 7.25 shows the DMA-end interrupt logic. An interrupt is requested whenever DTE = 0 and DTIE = 1. DTE DTIE DMA-end interrupt Figure 7.25 DMA-End Interrupt Logic The DMA-end interrupt for the B channels (DENDB) is unavailable in full address mode. The DTME bit does not affect interrupt operations. |
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