H83069RF datasheet(273/1003 Pages) RENESAS

273 / 1003 page

Rev. 5.0, 09/04, page 251 of 978

Table 7.14

Address Ranges Specifiable in MAR and IOAR

1-Mbyte Mode

16-Mbyte Mode

MAR

H'00000 to H'FFFFF

(0 to 1048575)

H'000000 to H'FFFFFF

(0 to 16777215)

IOAR

H'FFF00 to H'FFFFF

(1048320 to 1048575)

H'FFFF00 to H'FFFFFF

(16776960 to 16777215)

MAR bits 23 to 20 are ignored in 1-Mbyte mode.

7.6.8

Bus Cycle when Transfer is Aborted

When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME

bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead

cycle may occur. This dead cycle does not update the halted channel’s address register or counter

value. Figure 7.27 shows an example in which an auto-requested transfer in cycle-steal mode on

channel 0 is aborted by clearing the DTE bit in channel 0.

Address bus

HWR, LWR

CPU cycle

DMAC cycle

CPU cycle

DMAC

cycle

CPU cycle

DTE bit is

cleared

Figure 7.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode

7.6.9

Transfer Requests by A/D Converter

When the A/D converter is set to scan mode and conversion is performed on more than one

channel, the A/D converter generates a transfer request when all conversions are completed. The

converted data is stored in the appropriate ADDR registers. Block transfer mode and full address

mode should therefore be used to transfer all the conversion results at one time.

H83069RF Datasheet(PDF) 273 Page - Renesas Technology Corp