H83069RF datasheet(296/1003 Pages) RENESAS

296 / 1003 page

Rev. 5.0, 09/04, page 274 of 978

8.7.2

Table 8.10 summarizes the registers of port 6.

Table 8.10

Port 6 Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'EE005

Port 6 data direction register

P6DDR

H'80

H'FFFD5

Port 6 data register

P6DR

R/W

H'80

Note:

Lower 20 bits of the address in advanced mode.

Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select

input or output for each pin in port 6.

Bit 7 is reserved. It is fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

P6 DDR

Port 6 data direction 6 to 0

These bits select input or output for port 6 pins

Reserved bit

Modes 1 to 5 (Expanded Modes): P6

7 functions as the clock output pin (φ) or an input port. P67 is

the clock output pin (

φ) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input

port if this bit is set to 1.

6 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the

settings of bits P6

6DDR to P63DDR.

2 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output

ports. For the method of selecting the pin functions, see table 8.11.

When P6

2 to P60 function as input/output ports, the pin becomes an output port if the

corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.

Mode 7 (Single-Chip Mode): P6

7 functions as the clock output pin (φ) or an input port.

6 to

0 function as generic input/output ports.

7 is the clock output pin (φ) if the PSTOP bit in

MSTCRH is cleared to 0, and an input port if this bit is set to 1 (initial value). A pin in port 6

becomes an output port if the corresponding bit of P6

6DDR to P60DDR is set to 1, and an input

port if this pin is cleared to 0.

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