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TAS3218IPZP Datasheet(PDF) 46 Page - Texas Instruments |
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TAS3218IPZP Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 79 page  RESET TIMING WITH RESPECT TO DVDD POWER GOOD RESET TIMING SERIAL AUDIO PORT SLAVE MODE SIGNALS SERIAL AUDIO PORT MASTER MODE SIGNALS TAS3218 SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com See Figure 34 PARAMETER MIN TYP MAX UNIT tpgw(L) Minimum pulse duration, RESET low following DVDD = 3.3 V 100 ms control signal parameters over recommended operating conditions (unless otherwise noted), see Figure 35 PARAMETER MIN TYP MAX UNIT trDMSTATE Time to outputs inactive 100 s twRESET Pulse duration, RESET active 200 ns trEMSTATE Time to enable I 2C <50 ms over recommended operating conditions (unless otherwise noted), see Figure 36 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLRCLK Frequency, LRCLKIN (FS) 32 48 kHz twSCLKIN Pulse duration, SCLKIN high(1) 0.4 tcyc 0.6 tcyc ns fSCLKIN Frequency, SCLKIN 64 Fs MHz tcyc Cycle time, SCLKIN(1) 1/64 Fs ns Propagation delay, SCLKIN falling edge to tpd1 16 ns SDOUT tsu1 Setup time, LRCLK to SCLKIN rising edge 10 ns th1 Hold time, LRCLK from SCLKIN rising edge 5 ns tsu2 Setup time, SDIN to SCLKIN rising edge 10 ns th2 Hold time, SDIN from SCLKIN rising edge 5 ns Propagation delay, SCLKIN falling edge to tpd2 SCLKOUT = SCLKIN 15 ns SCLKOUT falling edge (1) tcyc = 1/ fSCLKIN over recommended operating conditions (unless otherwise noted), see Figure 37 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLRCLK Frequency LRCLKOUT 48 kHz trLRCLK Rise time, LRCLKOUT CL = 30 pF 12 ns tfLRCLK Fall time, LRCLKOUT CL = 30 pF 12 ns fSCLKOUT Frequency, SCLKOUT(1) 64 Fs MHz trSCLKOUT Rise time, SCLKOUT CL = 30 pF 12 ns tfSCLKOUT Fall time, SCLKOUT CL = 30 pF 12 ns Propagation delay, SCLKOUT falling edge to tpd1 5 ns LRCLKOUT edge Propagation delay, SCLKOUT falling edge to tpd2 5 ns SDOUT12 tsu Setup time, SDIN to SCLKOUT rising edge 25 ns th Hold time, SDIN from SCLKOUT rising edge 30 ns (1) Typical duty cycle is 50/50. 46 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TAS3218 |
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