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TAS3218IPZP Datasheet(PDF) 11 Page - Texas Instruments |
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TAS3218IPZP Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 79 page ![]() LRCLK SCLK 2-Channel Left-Justified Stereo Input Left Channel Right Channel LSB MSB MSB LSB 32 clks 32 clks 24-Bit Mode 20-Bit Mode 16-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 LRCLK SCLK 2-Channel Right-Justified (Sony Format) Stereo Input Left Channel Right Channel LSB MSB MSB LSB 32 clks 32 clks 24-Bit Mode 20-Bit Mode 16-Bit Mode 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 23 22 21 20 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 19 18 17 16 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 15 14 13 10 9 8 7 6 5 4 3 2 1 0 12 11 SAP Input and Output Normalization TAS3218 www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008 Discrete Left-Justified Left-justified (LJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 Fs is used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will mask unused trailing data bit positions. A. All data are presented in 2's complement form with MSB first. Figure 6. SAP Left-Justified 64 Fs Format Discrete Right-Justified Right Justified (RJ) timing uses an L/RCLK to define when the data being transmitted is for the left channel and when it is for the right channel. The L/RCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64 Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS3218 will mask unused leading data bit positions. A. All data are presented in 2's complement form with MSB first. Figure 7. SAP Right-Justified 64 Fs Format The TAS3218 supports SAP input and SAP output normalization. This supports simultaneous output to left-justified and I2S devices. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TAS3218 |
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