AD5763CSUZ datasheet(19/31 Pages) AD

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Preliminary Technical Data

AD5763

Rev. PrA | Page 19 of 31

68HC111

MISO

SYNC

SDIN

SCLK

MOSI

SCK

PC7

PC6

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SDIN

1ADDITIONAL PINS OMITTED FOR CLARITY

AD57631

Figure 32. Daisy-Chaining the AD5763

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be

used to daisy-chain several devices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

number of serial interface lines. The first falling edge of SYNC

starts the write cycle. The SCLK is continuously applied to the

input shift register when SYNC is low. If more than 24 clock

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. This data is clocked out on the rising

edge of SCLK and is valid on the falling edge. By connecting the

SDO of the first device to the SDIN input of the next device in

the chain, a multidevice interface is constructed. Each device in

the system requires 24 clock pulses. Therefore, the total number

of clock cycles must equal 24N, where N is the total number of

AD5763 devices in the chain. When the serial transfer to all

devices is complete, SYNC is taken high. This latches the input

data in each device in the daisy chain and prevents any further

data from being clocked into the input shift register. The serial

clock can be a continuous or a gated clock.

A continuous SCLK source can only be used if SYNC is held

low for the correct number of clock cycles. In gated clock mode,

a burst clock containing the exact number of clock cycles must

be used and SYNC must be taken high after the final clock to

latch the data.

Readback Operation

Before a readback operation is initiated, the SDO pin must be

enabled by writing to the function register and clearing the

SDO DISABLE bit; this bit is cleared by default. Readback mode

is invoked by setting the R/W bit = 1 in the serial input register

write. With R/W = 1, Bit A2 to Bit A0, in association with Bit

REG2, Bit REG1, and Bit REG0, select the register to be read.

The remaining data bits in the write sequence are don’t care.

During the next SPI write, the data appearing on the SDO

output contain the data from the previously addressed register.

For a read of a single register, the NOP command can be used

in clocking out the data from the selected register on SDO. The

readback diagram in Figure 4 shows the readback sequence. For

example, to read back the fine gain register of Channel A on the

AD5763, the following sequence should be implemented:

1. Write 0xA0XXXX to the AD5763 input register. This

configures the AD5763 for read mode with the fine gain

DB15 to DB0, are don’t cares.

2. Follow this with a second write, an NOP condition,

0x00XXXX. During this write, the data from the fine gain

out contain the data from the fine gain register in Bit DB5 to

Bit DB0.

SIMULTANEOUS UPDATING VIA LDAC

Depending on the status of both SYNC and LDAC, and after

data has been transferred into the input register of the DACs,

there are two ways in which the DAC registers and DAC

outputs can be updated.

Individual DAC Updating

In this mode, LDAC is held low while data is being clocked into

the input shift register. The addressed DAC output is updated

on the rising edge of SYNC.

Simultaneous Updating of All DACs

In this mode, LDAC is held high while data is being clocked

into the input shift register. All DAC outputs are updated by

taking LDAC low any time after SYNC has been taken high.

The update now occurs on the falling edge of LDAC.

VOUT

DAC

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

VREFIN

SYNC

INPUT

SCLK

Figure 33. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

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