Preliminary Technical Data

AD5763

Rev. PrA | Page 21 of 31

FUNCTION REGISTER

The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine

the function addressed. The functions available via the function register are outlined in Table 10 and Table 11.

Table 10. Function Register Options

REG2

REG1

REG0

A2

A1

A0

DB15:DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

0

NOP, Data = Don’t Care

0

0

0

0

0

1

Don’t Care

Local-

Ground-

Offset Adjust

D1

Direction

D1

Value

D0

Direction

D0

Value

SDO

Disable

0

0

0

1

0

0

CLR, Data = Don’t Care

0

0

0

1

0

1

LOAD, Data = Don’t Care

Table 11. Explanation of Function Register Options

Option

Description

NOP

No operation instruction used in readback operations.

Local-Ground-

Offset Adjust

Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust

function (default). Refer to Features section for further details.

D0/D1 Direction

Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the

Features section for further details.

D0/D1 Value

I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when

configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.

When enabled as inputs, these bits are don’t cares during a write operation.

SDO Disable

Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).

CLR

Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.

LOAD

Addressing this function updates the DAC registers and consequently the analog outputs.

DATA REGISTER

The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer

is to take place (see Table 9). The data bits are in positions DB15 to DB0 as shown in Table 12.

Table 12. Programming the AD5763 Data Register

REG2

REG1

REG0

A2

A1

A0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

DAC Address

16-Bit DAC Data

COARSE GAIN REGISTER

The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 9). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC

as shown in Table 13 and Table 14.

Table 13. Programming the AD5763 Coarse Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15 …. DB2

DB1

DB0

0

1

1

DAC Address

Don’t Care

CG1

CG0

Table 14. Output Range Selection

Output Range

CG1

CG0

±4.096 V (default)

0

0

±4.201 V

0

1

±4.331 V

1

0