AD7401A datasheet(17/20 Pages) AD

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AD7401A

Rev. 0 | Page 17 of 20

Z = one sample delay

MCLKOUT = modulators conversion bit rate

Z = one sample delay

WORD_CLK = output word rate

always @ (posedge mclk1 or posedge reset)

if (reset)

begin

/*initialize acc registers on reset*/

acc1 <= 0;

acc2 <= 0;

acc3 <= 0;

end

else

begin

/*perform accumulation process*/

acc1 <= acc1 + ip_data1;

acc2 <= acc2 + acc1;

acc3 <= acc3 + acc2;

end

always @ (posedge word_clk or posedge reset)

if(reset)

begin

acc3_d2 <= 0;

diff1_d <= 0;

diff2_d <= 0;

diff1 <= 0;

diff2 <= 0;

diff3 <= 0;

end

else

begin

diff1 <= acc3 - acc3_d2;

diff2 <= diff1 - diff1_d;

diff3 <= diff2 - diff2_d;

acc3_d2 <= acc3;

diff1_d <= diff1;

diff2_d <= diff2;

end

/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)

always @ (negedge mclk1 or posedge reset)

if (reset)

word_count <= 0;

else

word_count <= word_count + 1;

/* Clock the Sinc output into an output

always @ (word_count)

word_clk <= word_count[7];

/*DIFFERENTIATOR ( including decimation

stage)

Perform the differentiation stage (FIR) at a

lower speed.

WORD_CLK

DATA

DIFF3

Figure 29. Clocking Sinc Output into an Output Register

WORD_CLK

ACC3

DIFF1

DIFF3

–

DIFF2

Z–1

–

Z–1

WORD_CLK = output word rate

always @ (posedge word_clk)

begin

Figure 28. Differentiator

DATA[15] <= diff3[23];

DATA[14] <= diff3[22];

DATA[13] <= diff3[21];

DATA[12] <= diff3[20];

DATA[11] <= diff3[19];

DATA[10] <= diff3[18];

DATA[9]

<= diff3[17];

DATA[8]

<= diff3[16];

DATA[7]

<= diff3[15];

DATA[6]

<= diff3[14];

DATA[5]

<= diff3[13];

DATA[4]

<= diff3[12];

DATA[3]

<= diff3[11];

DATA[2]

<= diff3[10];

DATA[1]

<= diff3[9];

DATA[0]

<= diff3[8];

end

endmodule

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