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TLV320ADC3101IRGER Datasheet(PDF) 49 Page - Texas Instruments |
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TLV320ADC3101IRGER Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 84 page  TLV320ADC3101 www.ti.com ........................................................................................................................................................................................... SLAS553 – NOVEMBER 2008 Page 0/Register 32: CODEC Secondary Interface Control 2 Reset Values BIT DESCRIPTION Value D7–D4 0 All values Reserved don't write any value other than reset value. D3 0 0 Primary BCLK is used for Audio Interface and Clocking 1 Secondary BCLK is used for Audio Interface and Clocking D2 0 0 Primary WCLK is used for Audio Interface and Clocking 1 Secondary WCLK is used for Audio Interface and Clocking D1–D0 0 All values Reserved don't write any value other than reset value. Page 0/Register 33: CODEC Secondary Interface Control 3 Reset Values BIT DESCRIPTION Value D7 0 0 Primary BCLK Output = Internally generated BCLK Clock 1 Primary BCLK Output = Secondary BCLK D6 0 0 Secondary BCLK Output = Primary BCLK 1 Secondary BCLK Output = Internally generated BCLK Clock D5–D4 0 0 Reserved. Do not use. 1 Primary WCLK Output = Internally generated ADC_FS Clock 2 Primary WCLK Output = Secondary WCLK 3 Reserved. Do not use. D3–D2 0 0 Secondary WCLK Output = Primary WCLK 1 Reserved. Do not use. 2 Secondary WCLK Output = Internally generated ADC_FS Clock 3 Reserved. Do not use. D2–D0 0 All values Reserved don't write any value other than reset value. Page 0/Register 34: I2S Sync Bit Reset Values Description Value D7 0 0 Internal logic is enabled to detect the I2C hang and react accordingly. 1 Internal logic is disabled to detect the I2C hang. D6(1) 0 0 I2C hang is not detected. 1 I2C hang detected flag. Once set get cleared only after reading this register. D5 0 0 I2C general call address will be ignored. 1 Device will accept I2C general call address. D4 0 All values Reserved don't write any value other than reset value. D3 0 All values Reserved don't write any value other than reset value. D2 0 All values Reserved don't write any value other than reset value. D1 0 0 Re-sync logic is Disabled for ADC 1 Re-Sync Stereo ADC with Codec Interface if the group delay changed by more than ±ADCFS/4. D0 0 0 Re-Sync is done without soft-muting the channel for ADC 1 Re-Sync is done by internally soft-muting the channel for ADC (1) Read Only Bits...Writing any value to this will not be used anywhere. Page 0/Register 35: Reserved Bit Reset Values Description Value D7–D0 X All values Reserved don't write to this register. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Link(s) :TLV320ADC3101 |
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