TLV320ADC3101IRGER datasheet(21/84 Pages) TI

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LD(n)

LD (n+1)

RD(n)

LEFTCHANNEL

RIGHTCHANNEL

LD(n)=n'thsampleofleftchanneldate

RD(n)=n'thsampleofrightchanneldate

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2 n-3

DSP Mode

LD(n)

LD(n+1)

RD(n)

LEFTCHANNEL

RIGHTCHANNEL

LD(n)=n'thsampleofleftchanneldate

RD(n)=n'thsampleofrightchanneldate

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2 n-3

LD(n)

LD (n+1)

RD (n)

LEFTCHANNEL

RIGHTCHANNEL

LD(n)=n'thsampleofleftchanneldate

RD(n)=n'thsampleofrightchanneldate

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2 n-3

TLV320ADC3101

www.ti.com ........................................................................................................................................................................................... SLAS553 – NOVEMBER 2008

Figure 25. I2S Mode with Offset1=0, Bit Clock Invert

For I2S mode, the number of bit-clock’s per channel should be greater than or equal to the programmed

word-length of the data. Also the programmed offset value should be less than the number of bit-clocks per

frame by at least the programmed word-length of the data.

In DSP mode, the falling edge of the word clock starts the data transfer with the left channel data first and is

immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 26. DSP Mode

Figure 27. DSP Mode with Offset1=1

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