BLF573S datasheet(8/14 Pages) NXP

8 / 14 page

BLF573S_1

Preliminary data sheet

Rev. 01 — 8 December 2008

8 of 14

NXP Semiconductors

BLF573S

HF / VHF power LDMOS transistor

8.1.2 2-Tone CW

8.2 Test circuit

VDS = 50 V; IDq = 900 mA; f1 = 224.95 MHz;

f2 = 225.05 MHz.

VDS = 50 V; f1 = 224.95 MHz; f2 = 225.05 MHz.

(1) IDq = 500 mA

(2) IDq = 700 mA

(3) IDq = 900 mA

(4) IDq = 1100 mA

(5) IDq = 1300 mA

(6) IDq = 1500 mA

(7) IDq = 1700 mA

(8) IDq = 1800 mA

Fig 7.

Power gain and drain efﬁciency as functions of

peak envelope load power; typical values

Fig 8.

Third order intermodulation distortion as a

function of peak envelope load power; typical

values

PL(PEP) (W)

500

400

200

300

100

001aaj146

(dB)

ηD

(%)

ηD

PL(PEP) (W)

500

400

200

300

100

001aaj147

−40

−60

−20

IMD3

(dBc)

−80

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

Table 9.

List of components

For production test circuit, see Figure 9 and Figure 10.

Printed-Circuit Board (PCB): Rogers 5880;

εr = 2.2 F/m; height = 0.79 mm; Cu (top/bottom metallization);

thickness copper plating = 35

µm.

Component

Description

Value

Remarks

ferrite SMD bead

100

Ω; 100 MHz

Ferroxcube BDS3/3/8.9-4S2 or equivalent

C1, C18

multilayer ceramic chip capacitor

100 pF

[1]

multilayer ceramic chip capacitor

39 pF

[1]

C3, C4

multilayer ceramic chip capacitor

180 pF

[1]

C5, C6, C7

multilayer ceramic chip capacitor

220 pF

[1]

C8, C20

multilayer ceramic chip capacitor

1 nF

[1]

multilayer ceramic chip capacitor

4.7

µF

TDK C4532X7R1E475MT020U or equivalent

C10

multilayer ceramic chip capacitor

30 pF

[1]

C11, C12, C13 multilayer ceramic chip capacitor

51 pF

[1]

C14

multilayer ceramic chip capacitor

43 pF

[1]

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