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CS5460A Datasheet(PDF) 40 Page - Cirrus Logic |
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CS5460A Datasheet(HTML) 40 Page - Cirrus Logic |
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40 / 54 page ![]() CS5460A 40 DS487F4 4.1.5 Power-Down The device has two power-down states to conserve power. If the chip is put in stand-by state, all circuitry except the analog/digital clock generators is turned off. In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Waking up the CS5460A out of sleep state requires more time than waking the device out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal. [S1 S]0 Power-down state 00 = Reserved 01 = Halt and enter stand-by power saving state. This state allows quick power-on time 10 = Halt and enter sleep power saving state. This state requires a slow power-on time 11 = Reserved 4.1.6 Calibration The device has the capability of performing a system AC offset calibration, DC offset calibration, AC gain calibration, and DC gain calibration. Calibration can be done on the voltage channel, the current channel, or both channels at the same time. Offset and gain calibrations should NOT be performed at the same time (must do one after the oth- er). For a given application, if DC gain calibrations are performed, then AC gain calibration should not be performed (and vice-versa). The proper input voltages must be supplied to the device before initiating calibration. [V I] Designates calibration channel 00 = Not allowed 01 = Calibrate the current channel 10 = Calibrate the voltage channel 11 = Calibrate voltage and current channel simultaneously R Specifies AC calibration (R=1) or DC calibration (R=0) G Designates gain calibration 0 = Normal operation 1 = Perform gain calibration O Designates offset calibration 0 = Normal operation 1 = Perform offset calibration B7 B6 B5 B4 B3 B2 B1 B0 1 0 0S1 S00 0 0 B7 B6 B5 B4 B3 B2 B1 B0 11 0 V I R G O |
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