CS5461A datasheet(13/44 Pages) CIRRUS

13 / 44 page

CS5461A

DS661F2

4. THEORY OF OPERATION

The CS5461A is a dual-channel analog-to-digital con-

verter (ADC) followed by a computation engine that per-

forms

power

calculations

and

energy-to-pulse

conversion. The flow diagram for the two data paths is

depicted in Figure 2. The analog inputs are structured

with two dedicated channels, voltage and current, then

optimized to simplify interfacing to sensing elements.

The voltage-sensing element introduces a voltage

waveform on the voltage channel input VIN± and is sub-

ject to a gain of 10x. A second-order, delta-sigma mod-

ulator samples the amplified signal for digitization.

Simultaneously, the current-sensing element introduces

a voltage waveform on the current channel input IIN±

and is subject to the two selectable gains of the pro-

grammable gain amplifier (PGA). The amplified signal is

sampled by a fourth-order, delta-sigma modulator for

digitization. Both converters sample at a rate of

MCLK/8, the over-sampling provides a wide dynamic

range and simplified anti-alias filter design.

4.1 Digital Filters

The decimating digital filters on both channels are Sinc3

filters followed by 4th-order, IIR filters. The single-bit

data is passed to the low-pass decimation filter and out-

put at a fixed word rate. The output word is passed to

the IIR filter to compensate for the magnitude roll-off of

the low-pass filtering operation.

An optional digital High-pass Filter (HPF in Figure 2) re-

moves any DC component from the selected signal

path. By removing the DC component from the voltage

and/or the current channel, any DC content will also be

removed from the calculated active power as well. With

both HPFs enabled, the DC component will be removed

from the calculated VRMS and IRMS as well as the appar-

ent power.

When the HPF option is used in only one channel, the

APF (all pass filter) option can be applied to the other

channel to preserve the phase match between the two

channels.

4.2 Voltage and Current Measurements

The digital filter output word is then subject to a DC off-

set adjustment and a gain calibration (See Section 7.

System Calibration on page 35). The calibrated mea-

surement is available to the user by reading the instan-

taneous voltage and current registers.

The Root Mean Square (RMS) calculations are per-

formed on N instantaneous voltage and current sam-

ples, Vn and In respectively (where N is the cycle count),

using the formula:

and likewise for VRMS, using Vn. IRMS and VRMS are ac-

cessible by register reads, which are updated once ev-

ery cycle count (referred to as a computational cycle).

4.3 Power Measurements

The instantaneous voltage and current samples are

multiplied to obtain the instantaneous power (see Fig-

ure 2). The product is then averaged over N conver-

sions to compute active power and used to drive energy

pulse outputs E1, E2 and E3. Output E3 provides a uni-

form pulse stream that is proportional to the active pow-

er and is designed for system calibration.

VOLTAGE

SINC 3

V *

CURRENT

SINC 3

DELAY

REG

DELAY

REG

HPF

Option

RMS

IIR

I *

DCoff*

PGA

IIR

Energy-to-pulse

+ Σ

Configuration Register *

Digital Filter

HPF

Option

S *

2nd Order

∆Σ

Modulator

4th Order

∆Σ

Modulator

x10

ACoff*

√

Active

√

Poff *

SYSGain *

PC6 PC5 PC4 PC3 PC2 PC1 PC0

PulseRateE1,2 *

PulseRateE3 *

Energy-to-pulse

*DENOTES REGISTER NAME.

APF

Option

APF

Option

Figure 2. Data Flow.

RMS

–

∑

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