CS5461A datasheet(27/44 Pages) CIRRUS

27 / 44 page

CS5461A

DS661F2

iCPU

Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals

are sampled, the logic driven by CPUCLK should not be active during the sample edge.

0 = Normal operation (default)

1 = Minimize noise when CPUCLK is driving rising-edge logic

K[3:0]

Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal

clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-

tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.

6.2 Current and Voltage DC Offset Register ( IDCoff ,VDCoff )

Address: 1 (Current DC Offset); 3 (Voltage DC Offset)

Default = 0x000000

The DC Offset registers (IDCoff,VDCoff) are initialized to 0.0 on reset. When DC Offset calibration is performed, the

the calibration. This register may be read and stored for future system offset compensation. The value is repre-

sented in two's complement notation and in the range of -1.0

≤ I

DCoff, VDCoff < 1.0, with the binary point to the

right of the MSB.

6.3 Current and Voltage Gain Register ( Ign ,Vgn )

Address: 2 (Current Gain); 4 (Voltage Gain)

Default = 0x400000 = 1.000

The gain registers (Ign,Vgn) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,

the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of

the calibration. This register may be read and stored for future system gain compensation. The value is in the

range 0.0

≤ I

gn,Vgn < 3.9999, with the binary point to the right of the second MSB.

6.4 Cycle Count Register

Address: 5

Default = 0x000FA0 = 4000

Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,

the computation cycle frequency is (MCLK/K)/(1024

∗N). A one second computational cycle period occurs when

MCLK = 4.096 MHz, K = 1, and N = 4000.

MSB

LSB

-(20)2-1

2-2

2-3

2-4

2-5

2-6

2-7

.....

2-17

2-18

2-19

2-20

2-21

2-22

2-23

MSB

LSB

2-1

2-2

2-3

2-4

2-5

2-6

.....

2-16

2-17

2-18

2-19

2-20

2-21

2-22

MSB

LSB

223

222

221

220

219

218

217

216

.....

CS5461A Datasheet(PDF) 27 Page - Cirrus Logic

CS5461A Datasheet(HTML) 27 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL