2

MH1

4138G–AERO–05/04

Note:

1. Nominal 2 Input NAND Gate FO = 2 at 3 volts.

Design

Design Systems

Supported

Atmel supports several major software systems for design with complete macro cell

libraries, as well as utilities for checking the netlist and accurate pre-route delay

simulations.

The following design systems are supported:

Table 1. List of Available MH1 Matrices

Device

Number

Typical Routable

Gates

Max Pad Count

Max

I/O Count

Gate

Max Sites

Count

MH1099

519,000

332

324

170 ps

920 385

MH1156

764,000

412

404

170 ps

1 447 975

MH1242

1,198,000

512

504

170 ps

2 275 377

MH1332

1,634,000

596

588

170 ps

3 098 804

Table 2. Design Systems Supported

System

Available Tools

Verilog-XL™ - Verilog Simulator

Mentor/Model Tech™

Modelsim Verilog and VHDL (VITAL) Simulator

DFT - Scan Insertion and ATPG, BIST

Synopsys

®

Design Compiler

Primetime™ - Static Path

Formality