5

MH1

4138G–AERO–05/04

Pin Definition

Requirements

The corner pads are reserved for Power and Ground only. All other pads are fully pro-

grammable as Input, Output, Bidirectional, Power or Ground. When implementing a

design with 5V tolerant buffers, one buffer site must be reserved for the V

is used to distribute power to the buffers.

Figure 1. Gate Array

Figure 2. Embedded Array

I/O Site: Pad and Sub-

Sections

The I/O sites can be configured as input, output, 3-state output and bidirectional buffers,

each with pull-up or pull-down capability, if required, by utilizing their corresponding sub-

section. Bidirectional buffers are the result of an input and output buffers placed in adja-

cent sub-sections in the same I/O site. Special buffers may require multiple I/O sites.

Oscillators require 2 I/O sites, each power and ground pin utilizes one I/O site.

PCI Buffers

PCI compatible input and output buffers are available for each bias voltage, 3V and 5V.

LVDS Buffers

Each LVDS buffer uses 2 I/O sites.

LVDS drivers are specific for each bias voltage and require one external current bias

resistor per chip; LVDS receiver is the same for all bias voltages and requires 1 external

line matching 100

Memory Blocks

Memory blocks can be either synthesized on gates (when smaller than 8 bits) or com-

piled and embedded in the array itself.

SRAM

Core

Core

Standard

Gate Array

Architecture