6

MH1

4138G–AERO–05/04

ASIC Design

Translation

Atmel has successfully translated existing designs from most major ASIC vendors (LSI

These designs have been optimized for speed and gate count and modified to add logic

or memory, or replicated for a pin-to-pin compatible, drop-in replacement.

Design Entry

Design entry is performed by the customer using an Atmel ASIC library. A complete

netlist and vector set must then be provided to Atmel. Upon acceptance of this data set,

Atmel continues with the standard design flow.

FPGA and PLD

Conversions

Atmel has successfully translated existing FPGA/PLD designs from most major ven-

convert from an FPGA/PLD to a gate array. Conversion of high volume devices for a

single or combined design is cost effective. Performance can often be optimized for

speed or low power consumption. Several FPGA/PLDs can be combined onto a single

chip to minimize cost while reducing on-board space requirements. Finally, in situations

where an FPGA/PLD was used for fast cycle time prototyping, a gate array may pro-

vide a lower cost answer for long-term volume production.

MH1 Series Cell

Library

Atmel’s MH1 Series gate arrays make use of an extensive library of macro cell struc-

tures, including logic cells, buffers and inverters, multiplexers, decoders, and I/O

options. Soft macros are also available.

The MH1 Series PLL operates at frequencies of up to 250 MHz with minimal phase error

and jitter, making it ideal for frequency synthesis of high speed on-chip clocks and chip

to chip synchronization.

These cells are well characterized by use of SPICE modeling at the transistor level, with

performance verified on manufactured test arrays. Characterization is performed over

the rated temperature and voltage ranges to ensure that the simulation accurately pre-

dicts the performance of the finished product.

Cells

Number of Cells

Logic Cells

95

I/O Buffers

3V or 2.5V or 3.3V

5V Tolerant

5V Compliant

110

36

70

Specific Cells

LVDS, PCI

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