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4110K–AERO–11/07

MH1RT

Design Flow

and Tools

Atmel’s design flow for Gate Array/Embedded Array is structured to allow the designer to consol-

idate the greatest number of system components possible onto the same silicon chip, using

available third party design tools. Atmel’s cell library reflects silicon performance over extremes

of temperature, voltage, and process, and includes the effects of metal loading, inter-level

capacitance, and edge rise and fall times. The Design Flow includes clock tree synthesis to min-

imize skew and latency. RC extraction is performed on final design database and incorporated

into the timing analysis.

The Typical Gate Array/Embedded Array Design Flow, shown on page 4, provides a pictorial

description of the typical interaction between Atmel’s Gate Array/Embedded Array design staff

and the customer. Atmel will deliver design kits to support the customer’s synthesis, verification,

floorplanning, and SCAN insertion activities. Tools such as Synopsys Synthesis, Cadence and

Mentor Logic Simulators are used, and many others are available. Should a design include

embedded memory or an embedded core, Atmel needs to understand the partition of the Array,

and define the location of the memory blocks and/or cores (preliminary place and route) so that

an underlayer layout model can be created (Base Wafer).

Following a Preliminary Design Review, so called Logic Review, the design is routed, and post-

route RC data is extracted. Following post-route verification and a Final Design Review, so

called Design Review, the design is taped out for fabrication.

The purpose of these reviews is to check the conformity of the design to Atmel rules, and

acknowledge it in formal documents.