5

4110K–AERO–11/07

MH1RT

Pin Definition

Requirements

The corner pads are reserved for Power and Ground only. All other pads are fully programmable

as Input, Output, Bidirectional, Power or Ground. When implementing a design with 5V compli-

the buffers.

Figure 2. Gate Array

Figure 3. Embedded Array

I/O Site: Pad and

Sub-Sections

The I/O sites can be configured as input, output, 3-state output and bidirectional buffers, each

with pullup or pulldown capability, if required, by utilizing their corresponding sub-section. Bidi-

rectionnal buffers are the result of an input and output buffers placed in adjacent sub-sections in

the same I/O site. Special buffers may require multiple I/O sites. Oscillators require 2 I/O sites,

each power and ground pin utilizes one I/O site.

PCI Buffers

PCI compatible input and output buffers are available for each bias voltage, 3V and 5V.

LVDS Buffers

Each LVDS buffer uses 2 I/O sites.

LVDS drivers are specific for each bias voltage and require one external current bias resistor per

resistor per receiver.

Cold Sparing

It is the use of twice the same chip, A1 and A2, A1 ON and A2 OFF, with all signal pins/pads

connected by pairs, A1I1 with A2I1, A101 with A201,...

SRAM

Core

Core

Standard

Gate Array

Architecture