ACS8525P datasheet(19/112 Pages) SEMTECH

19 / 112 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3.01/August 2005 © Semtech Corp.

Page 19

www.semtech.com

ACS8525 LC/P

An Early/Late phase detector for fine resolution

A multi-cycle phase detector for large input jitter

tolerance (up to 8191 UI), which captures and

remembers phase differences of many cycles

between input and feedback clocks.

The phase detectors can be configured to be immune to

occasional missing input clock pulses by using nearest

edge detection (±180°capture) or the normal

± 360° phase capture range which gives frequency

locking. The device will automatically switch to nearest

edge locking when the multi-UI phase detector is not

enabled, and the other phase detectors have detected

that phase lock has been achieved. It is possible to

disable the selection of nearest edge locking via Reg. 03

Bit 6 (set to 1). In this setting, frequency locking will

always be enabled.

The balance between the first two types of phase detector

employed can be adjusted via Reg. 6A to 6D. The default

settings should be sufficient for all modes. Adjustment of

these settings affects only small signal overshoot and

bandwidth.

The multi-cycle phase detector (wide-range) is enabled via

Reg. 74, Bit 6 set to 1 and the range is set in exponentially

increasing steps from ±1 UI up to 8191 UI via Reg. 74,

Bits [3:0].

When this detector is enabled it keeps a track of the

correct phase position over many cycles of phase

difference to give excellent jitter tolerance. This provides

an alternative to switching to Lock8k mode as a method

of achieving high jitter tolerance.

An additional control (Reg. 74 Bit 5) enables the

multi-phase detector value to be used in the final phase

value as part of the DPLL loop. When enabled by setting

High, the multi cycle phase value will be used in the loop

and gives faster pull-in (but more overshoot). The

characteristics of the loop will be similar to Lock8k mode

where again large input phase differences contribute to

the loop dynamics. Setting the bit Low only uses a max

figure of 360° in the loop and will give slower pull-in but

gives less overshoot. The final phase position that the

loop has to pull in to is still tracked and remembered by

the multi-cycle phase detector in either case.

Phase Lock/Loss Detectors

Phase lock detection is handled in several ways. Phase

loss can be triggered from:

The fine phase lock detector, which measures the

phase between input and feedback clock

The coarse phase lock detector, which monitors whole

cycle slips

Detection that the DPLL is at min. or max. frequency

Detection of no activity on the input

Each of these sources of phase loss indication is

individually enabled via register bits (see Reg. 73 and 74).

Phase lock or lost is used to determine whether to switch

to nearest edge locking and whether to use acquisition or

normal bandwidth settings for the DPLL. Acquisition

bandwidth is used for faster pull-in from an unlocked

state.

The coarse phase lock detector detects phase differences

of n cycles between input and feedback clocks, where n is

set by Reg. 74 Bits [3:0]; the same register that is used for

the coarse phase detector range, since these functions go

hand in hand. This detector may be used in the case

where it is required that a phase loss indication is not

given for reasonable amounts of input jitter and so the

fine phase loss detector is disabled and the coarse

detector is used instead.

Phase Compensation Functions

The ACS8525 has the following phase compensation

functions and controls:

Phase Build-out (PBO)

PBO Phase Offset

Input-to-Output Phase Adjustment

Phase Build-out

Phase Build-out (PBO) is the function to minimize phase

transients on the output SEC clock during input reference

switching. If the currently selected input reference clock

source is lost (due to a short interruption or complete loss

of reference), the next highest priority SEC will be

selected, and a PBO event triggered. When a PBO event is

triggered, the device enters a temporary Holdover state.

When in this temporary state, the phase of the input

reference is measured, relative to the output. The device

then automatically accounts for any measured phase

difference and adds the appropriate phase offset into the

DPLL to compensate.

Following a PBO event, whatever the phase difference on

change of input, the output phase transient is minimized

to be typically less than ±2.5 ns (in digital feedback

mode).

On the ACS8525, PBO can be enabled, disabled or frozen

using the Serial interface. By default, it is enabled. When

ACS8525P Datasheet(PDF) 19 Page - Semtech Corporation

ACS8525P Datasheet(HTML) 19 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL