ACS8946 datasheet(3/40 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 3/November 2006 © Semtech Corp.

Page 3

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ACS8946 JAM PLL

Figure 2 ACS8946 Pin Diagram

Note...A= Analog, I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD =

LVTTL/LVCMOS input with pull-down resistor.

Pin Diagram

Pin Description

Table 1 Power Pins

Pin No.

Symbol

I/O

Type

Description

1, 4,

7, 10

VDDO1, VDDO2,

VDDO3, VDDO4

Supply Voltage: Independent supplies to power each clock output (differential pair of

pins) OUT1N/P to OUT4N/P respectively. +3.3 Volts ±5%. To disable an output and save

power, tie associated VDD to 0V.

VDDADIV

Supply Voltage: Supply for internal Dividers in VCO loop, kept as an isolated supply to

allow for low supply noise for the output divider stages. +3.3 Volts ±5%.

VDDP1

Supply Voltage: Supply to differential inputs, alarm and config. pins. +3.3 Volts ±5%.

VDDP2

Supply Voltage: Supply to Sync input and Sync output pins, rate selection pins, input

selection pins and reset pin. +3.3 Volts ±5%.

VDDARF

Supply Voltage: Supply for phase and frequency detector (PFD), kept as an isolated

supply to allow for low supply noise. +3.3 Volts ±5%.

VDDOSC

Supply Voltage: Supply input to the internal VCO. +3.3 Volts +5/-10%.

VSSOSC

Supply Ground: 0 V for the internal VCO.

VSS0

Supply Ground: Common 0 V.

This is the central leadframe pad on the underneath of the package.

F8944_D_002PINDIAG_01

VDDO1

OUT1N

OUT1P

VDDO2

OUT2N

VDDO3

OUT3N

OUT3P

10 VDDO4

11 OUT4N

12 OUT4P

OUT2P

VCN

VCP

VDDARF

AUTO_SEL

SEL_CLK2

CLK2P

CLK2N

VDDP1

CLK1P

CLK1N

VDDADIV

CFG_IN7

ACS8946

Connect large central

pad (Pin 49 VSSO) to GND

Dimensions: 7 mm x 7 mm

Lead Pitch: 0.5 mm

(Leads centered on package)

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