ATA5423-PLSW datasheet(58/100 Pages) ATMEL

58 / 100 page

4841D–WIRE–10/07

ATA5423/ATA5425/ATA5428/ATA5429

Figure 9-6.

Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)

Figure 9-7.

Timing Diagram for Failed Bit Check (Condition: CV_Lim

≥ Lim_max)

9.1.6

Duration of the Bit Check

If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers

random signals. The bit check is a statistical process and T

Bit-check varies for each check. There-

fore, an average value for T

Bit-check is given in the electrical characteristics. TBit-check depends on

the selected bit-rate range and on T

XDCLK. A higher bit-rate range causes a lower value for

Bit-check, resulting in a lower current consumption in RX polling mode.

Start-up mode

Sleep

Bit_check

Startup_Sig_Proc

Bit check mode

Sleep mode

1/2 Bit

RX_ACTIVE

Demod_Out

Bit-check counter

Bit check

(Lim_min = 14, Lim_max = 24)

Bit check failed (CV_Lim < Lim_min)

1 23456 7 8 1 234 5 67 89 101112

Start-up mode

Sleep

Bit_check

Startup_Sig_Proc

Bit check mode

Sleep mode

1/2 Bit

RX_ACTIVE

Demod_Out

Bit-check counter

Bit check

(Lim_min = 14, Lim_max = 24)

Bit check failed (CV_Lim < Lim_min)

1 2345678 1234 567 89 101112

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ATA5423-PLSW Datasheet(PDF) 58 Page - ATMEL Corporation

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