4

4953D–AUTO–10/08

ATA6837 [Preliminary]

17

CS

Chip select input; 5V CMOS logic level input with internal pull up;

low = serial communication is enabled, high = disabled

18

CLK

Serial clock input; 5V CMOS logic level input with internal pull down;

19

DI

Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control

device; DI expects a 16-bit control word with LSB being transferred first

20

OUT6

Output 6; see pin 1

21

OUT6 SENSE Only for testability in final test

22

OUT5 SENSE Only for testability in final test

23

OUT5

Output 5; see pin 1

24

NC

Internal bond to GND

Table 2-1.

Pin Description QFN24 (Continued)

Pin

Symbol

Function