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AT90USB646 Datasheet(PDF) 259 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 259 Page - ATMEL Corporation |
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259 / 459 page ![]() 259 7593H–AVR–11/08 ATmega32U6/AT90USB64/128 21.9 OTG timers customizing It is possible to refine some OTG timers thanks to the OTGTCON register that contains the PAGE bits to select the timer and the VALUE bits to adjust the value. User should refer to lastest releases of the OTG specification to select compliant timings. • PAGE=00b: AWaitVrise time-out. [OTG]. In Host mode, once VBUSREQ has been set to “1”, if no VBUS is detected on VBUS pin after this AWaitVrise delay then the VBERRI error flag is set. – VALUE=00bTime-out is set to 20 ms – VALUE=01bTime-out is set to 50 ms – VALUE=10bTime-out is set to 70ms – VALUE=11bTime-out is set to 100 ms • PAGE=01b: VbBusPulsing. [OTG]. In Device mode, this delay corresponds to the pulse duration on Vbus during a SRP. – VALUE=00bTime-out is set to 15 ms – VALUE=01bTime-out is set to 23 ms – VALUE=10bTime-out is set to 31 ms – VALUE=11bTime-out is set to 40 ms • PAGE=10b: PdTmOutCnt. [OTG]. In Device mode, when a SRP has been requested to be sent by the firmware, this delay is waited by the hardware after VBUS has gone below the “session_valid” threshold voltage and before initiating the first pulse. This delay should be considered as an approximation of USB lines discharge (pull-down resistors vs. line capacitance) in order to wait that VBUS has gone below the “b_session_end” threshold voltae, as defined in the OTG specification. – VALUE=00bTime-out is set to 93 ms – VALUE=01bTime-out is set to 105 ms – VALUE=10bTime-out is set to 118 ms – VALUE=11bTime-out is set to 131 ms •PAGE=11b: SRPDetTmOut. [OTG]. In Host mode, this delay is the minimum pulse duration required to detect and accept a valid SRP from a Device. – VALUE=00bTime-out is set to 10 us – VALUE=01bTime-out is set to 100 us – VALUE=10bTime-out is set to 1 ms – VALUE=11bTime-out is set to 11 ms 21.10 Plug-in detection The USB connection is detected by the VBUS pad, thanks to the following architecture: |
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