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AT90USB646 Datasheet(PDF) 305 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 305 Page - ATMEL Corporation |
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305 / 459 page  305 7593H–AVR–11/08 ATmega32U6/AT90USB64/128 Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent and the UNDERFI bit is set. • 4 - Reserved The value read from these bits is always 0. Do not set these bits. • 3-2 - DTSEQ1:0 - Toggle Sequencing Flag Set by hardware to indicate the PID data of the current bank: 00b Data0 01b Data1 1xb Reserved. For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the current bank. For IN Pipe, this value indicates the last data toggle received on the current bank. • 1-0 - NBUSYBK1:0 - Busy Bank Flag Set by hardware to indicate the number of busy bank. For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer. For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device. 00b All banks are free 01b 1 busy bank 10b 2 busy banks 11b Reserved. • 7-0 - INRQ7:0 - IN Request Number Before Freeze Enter the number of IN transactions before the USB controller freezes the pipe. The USB con- troller will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully performed. This register has no effect when the INMODE bit is set (infinite IN requests generation till the pipe is not frozen). • 7-6 - Reserved Bit 765432 10 INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 UPINRQX Read/Write RW RW RW RW RW RW RW RW Initial Value 000000 00 Bit 765 4 3 2 1 0 - COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL UPERRX Read/Write RW RW RW RW RW RW RW Initial Value 0 0 0 0 0 0 0 0 |
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