LT1637CS8 datasheet(11/16 Pages) LINER

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LT1637

1637fd

Supply Voltage

The positive supply pin of the LT1637 should be bypassed

with a small capacitor (about 0.01

µF) within an inch of the

pin. When driving heavy loads an additional 4.7

µF electro-

lytic capacitor should be used. When using split supplies,

the same is true for the negative supply pin.

The LT1637 is protected against reverse battery voltages

up to 25V. In the event a reverse battery condition occurs,

the supply current is typically less than 1nA.

When operating the LT1637 on total supplies of 30V or

more, the supply must not be brought up faster than 1

µs.

This is especially true if low ESR bypass capacitors are

used. A series RLC circuit is formed from the supply lead

inductance and the bypass capacitor. 5

Ω of resistance in

the supply or the bypass capacitor will dampen the tuned

circuit enough to limit the rise time.

Inputs

The LT1637 has two input stages, NPN and PNP (see the

Simplified Schematic), resulting in three distinct operat-

ing regions as shown in the Input Bias Current vs Common

Mode typical performance curve.

For input voltages about 0.9V or more below V+, the PNP

input stage is active and the input bias current is typically

– 20nA. When the input voltage is about 0.5V or less from

V+, the NPN input stage is operating and the input bias

current is typically 80nA. Increases in temperature will

cause the voltage at which operation switches from the

PNP stage to the NPN stage to move towards V+. The input

offset voltage of the NPN stage is untrimmed and is

typically 600

µV.

A Schottky diode in the collector of each NPN transistor of

the NPN input stage allows the LT1637 to operate with

either or both of its inputs above V+. At about 0.3V above

V+ the NPN input transistor is fully saturated and the input

bias current is typically 23

µA at room temperature. The

input offset voltage is typically 600

µV when operating

above V+. The LT1637 will operate with its input 44V above

V– regardless of V+.

APPLICATIO S I FOR ATIO

The inputs are protected against excursions as much as

22V below V – by an internal 1.3k resistor in series with

each input and a diode from the input to the negative

supply. There is no output phase reversal for inputs up to

5V below V –. There are no clamping diodes between the

inputs and the maximum differential input voltage is 44V.

Output

The output voltage swing of the LT1637 is affected by

input overdrive as shown in the typical performance

curves. When monitoring input voltages within 100mV of

V+, gain should be taken to keep the output from clipping.

The output of the LT1637 can be pulled up to 25V beyond

V+ with less than 1nA of leakage current, provided that V+

is less than 0.5V.

The normally reverse biased substrate diode from the

output to V– will cause unlimited currents to flow when the

output is forced below V–. If the current is transient and

limited to 100mA, no damage will occur.

The LT1637 is internally compensated to drive at least

200pF of capacitance under any output loading condi-

tions. A 0.22

µF capacitor in series with a 150Ω resistor

between the output and ground will compensate these

amplifiers for larger capacitive loads, up to 4700pF, at all

output currents.

Distortion

There are two main contributors of distortion in op amps:

output crossover distortion as the output transitions from

sourcing to sinking current and distortion caused by

nonlinear common mode rejection. Of course, if the op

amp is operating inverting there is no common mode

induced distortion. When the LT1637 switches between

input stages there is significant nonlinearity in the CMRR.

Lower load resistance increases the output crossover

distortion, but has no effect on the input stage transition

distortion. For lowest distortion the LT1637 should be

operated single supply, with the output always sourcing

current and with the input voltage swing between ground

and (V+ – 0.9V). See the Typical Performance Character-

istics curves.

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