STC4130 datasheet(13/44 Pages) CONNOR-WINFIELD

13 / 44 page

Data Sheet #: TM084

Page 13 of 44

Rev: P02

Date: 12/5/06

STC4130

Synchronous Clock for SETS

Data Sheet

Synchronized Mode

The Synchronized mode may be entered automati-

cally, when in the Automatic Reference Selection

mode (as shown in figure 4), or manually, by writing

to the T(0/4)_Manual_Active_Ref registers (0x1f/

0x3c), selecting a reference as well as the operating

mode.

Each DPLL’s loop bandwidth may be set indepen-

dently. Loop bandwidth is selectable from 90mHz to

107Hz by writing to the T(0/4)_Bandwidth registers

(0x1d/ 0x3a).

In the “Synchronized” mode, bit 0 of the T(0/

4)_Control_Mode registers (0x1c, 0x39) deter-

mines the output clock to input reference phase

alignment mode. In “Arbitrary” mode, the clock output

phase relationship relative to the reference input

phase is according to the initial start-up phase. In

“Phase Align” mode, the output clocks are phase

aligned to the selected reference. (It should be noted

that output-to-reference phase alignment is meaning-

full only in those cases where the output frequency

and reference are the same or related by a factor of

2n.)

When locked on an external reference, two holdover

histories are built, for use in Holdover mode:

1) Long-Term History – This is a long-term

averaged frequency of the selected external

reference, accumulated according to a sin-

gle-pole low pass filtering algorithm. The -

3dB point of the algorithm may be applica-

tion programmed for 9.7, 4.9, 2.4, 1.2, 0.61,

or 0.30 mHz, by writing to the T(0/

4)_HO_Ramp registers (0x30/ 0x4d). Inter-

nally, an express mode is used initially to

apply a lower time-constant to speed up the

history accumulation process. When a long

term history has been built, it is indicated as

available by the LHA bit 7 of the T(0/

4)_DPLL_Status

registers

(0x37/0x54).

Additionally, the application may flush/rebuild

this long-term history, by writing to the T(0/

4)_Accu_Flush registers (0x38, 0x55). The

long-term history is used when operating in

Holdover Mode, and may be read from the

T(0/4)_Long_Term_Accu_History

regis-

ters (0x24-0x27/ 0x41-0x44).

2) Short-Term History – The short term history

may be programmed for a -3dB point of 2.5,

1.24, 0.62, or 0.31 mHz by writing to the T(0/

4)_HO_Ramp registers (0x30/ 0x4d). The

short-term history is used, in the event of a

reference loss in manual reference selection

mode, and may be read from the

T(0/4)_Short_Term_Accu_History

regis-

ters (0x28-0x2b/ 0x45-ox48)

In manual mode selection, there are two special

cases of the Synchronized mode:

a) “Zombie” Mode – If the selected active reference

signal is lost, the DPLL output is generated according

to a short-term history.

b) Out of Pull-in Range Mode - If the selected refer-

ence exceeds the pull-in range as programmed by

the application, the DPLL output may be pro-

grammed to stay at the pull-in range limit, or to follow

the reference. This is programmed by writing to bit 5

of the T(0/4)_Control_Mode registers (0x1c/ 0x39),

specifying whether to follow or not follow a reference

that has exceded the pull-in range.

Additionally, when a device is operated as a slave in

a master/slave pair (by tying the T(0/4)_M/S pin low),

the device locks and phase align on the cross-cou-

pled SyncLinkTM data link signal on the (T0/

T4)_XSYNC_IN input.

When the device has locked on a reference, the

“SYNC” bit 0 is set in the T(0/4)_DPLL_Status regis-

ter (0x37/ 0x54). If synchronization is lost, the “LOL”

bit 2 is set in the T(0/4)_DPLL_Status register.

Holdover Mode

The application may select either of two sources of

frequency offset in Holdover mode, as determined by

writing bit 2 of the T(0/4)_Control_Mode registers

(0x1c/ 0x39):

a) Device Accumulated History Holdover Mode –

uses the long-term history accumulated by the

device to synthesize the DPLL output This is analo-

gous to the Freerun mode, except that the Holdover

algorithms effectively supply the “frequency offset”

from the holdover history.

b) User Supplied History Mode – The DPLL output

is synthesized according to an application supplied

frequency

offset,

provided

the

T(0/

4)_User_Accu_History registers (0x2c/ 0x49). To

facilitate the user’s accumulation of a holdover his-

tory, the user may read the short term history of the

active

reference

from

the

T(0/

4)_Shor_Term_Accu_History registers (0x28-0x2b/

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