STC4130 datasheet(39/44 Pages) CONNOR-WINFIELD

39 / 44 page

Data Sheet #: TM084

Page 39 of 44

Rev: P02

Date: 12/5/06

STC4130

Synchronous Clock for SETS

Data Sheet

Default value: 2.

CLK6_Sel, 0x5c (R/W)

Selects or disables the CLK6 output. Default = 0110, 2.048MHz:

Default value: 1.

CLK7_Sel, 0x5d (R/W)

Selects or disables the CLK7 output.

Default value: 2.

Intr_Event, 0x5e (R/W)

1DS3

2E3

Disabled

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x5c

Not used

CLK6 Select

0x5c, bits 3 ~ 0

CLK6 output

Disabled

2.048MHz

4.096MHz

8.192MHz

16.384MHz

32.768MHz

1.544MHz

3.088MHz

6.176MHz

12.352Hz

24.704MHz

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x5d

Not used

CLK7 Select

0x5d, bits 1 ~ 0

CLK7 output

Disabled

1T1

2E1

Disabled

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

0x5e

Event 7:

T4 cross

reference

changed

from non-

active to

active

Event 6:

T4 cross

reference

changed

from active

to non-

active

Event 5:

T4 DPLL

status

changed

Event 4:

T4 active

reference

changed in

auto selec-

tion mode

Event 3:

T0 cross

reference

changed

from non-

active to

active

Event 2:

T0 cross

reference

changed

from active

to non-

active

Event 1:

T0 DPLL

status

changed

Event 0:

T0 active

reference

changed in

auto selec-

tion mode

0x5b, bits 1 ~ 0

CLK5 output

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