eX Automotive Family FPGAs

v3.2

1-23

Enable-to-Pad, Z to L

4.5

ns

Enable-to-Pad Z to L—Low Slew

21.2

ns

Enable-to-Pad, Z to H

6.1

ns

Enable-to-Pad, L to Z

3.8

ns

Enable-to-Pad, H to Z

7.1

ns

Delta Delay vs. Load Low to High

0.058

ns/pF

Delta Delay vs. Load High to Low

0.028

ns/pF

Delta Delay vs. Load High to Low—Low Slew

0.090

ns/pF

Data-to-Pad Low to High

5.0

ns

Data-to-Pad High to Low

4.9

ns

Data-to-Pad High to Low—Low Slew

17.4

ns

Enable-to-Pad, Z to L

4.0

ns

Enable-to-Pad Z to L—Low Slew

17.4

ns

Enable-to-Pad, Z to H

5.0

ns

Enable-to-Pad, L to Z

5.0

ns

Enable-to-Pad, H to Z

4.8

ns

Delta Delay vs. Load Low to High

0.038

ns/pF

Delta Delay vs. Load High to Low

0.028

ns/pF

Delta Delay vs. Load High to Low—Low Slew

0.090

ns/pF

Table 1-17 • eX Family Timing Characteristics

‘Std.’ Speed

Parameter

Description

Min.

Max.

Units

Notes:

2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating

device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.

3. Clock skew improves as the clock network becomes more heavily loaded.

4. Delays based on 35 pF loading.