EX128-CS100 datasheet(13/49 Pages) ACTEL

13 / 49 page

eX Family FPGAs

v4.3

1-9

Boundary Scan Testing (BST)

All eX devices are IEEE 1149.1 compliant. eX devices offer

superior diagnostic and testing capabilities by providing

Boundary Scan Testing (BST) and probing capabilities.

These functions are controlled through the special test

pins (TMS, TDI, TCK, TDO and TRST). The functionality of

each pin is defined by two available modes: Dedicated

and Flexible, and is described in Table 1-4. In the

dedicated test mode, TCK, TDI, and TDO are dedicated

pins and cannot be used as regular I/Os. In flexible mode

(default mode), TMS should be set HIGH through a pull-

up resistor of 10 k

Ω. TMS can be pulled LOW to initiate

the test sequence.

Dedicated Test Mode

In Dedicated mode, all JTAG pins are reserved for BST;

designers cannot use them as regular I/Os. An internal

pull-up resistor is automatically enabled on both TMS

and TDI pins, and the TMS pin will function as defined in

the IEEE 1149.1 (JTAG) specification.

To select Dedicated mode, users need to reserve the JTAG

pins in Actel's Designer software by checking the

"Reserve JTAG" box in "Device Selection Wizard"

(Figure 1-12). JTAG pins comply with LVTTL/TTL I/O

specification regardless of whether they are used as a

user I/O or a JTAG I/O. Refer to the "3.3V LVTTL Electrical

Specifications" and "5.0V TTL Electrical Specifications"

on page 1-15 for detailed specifications.

Flexible Mode

In Flexible Mode, TDI, TCK and TDO may be used as

either user I/Os or as JTAG input pins. The internal

resistors on the TMS and TDI pins are disabled in flexible

JTAG mode, and an external 10 k

Ω pull-resistor to V

CCI is

required on the TMS pin.

To select the Flexible mode, users need to uncheck the

"Reserve JTAG" box in "Device Selection Wizard" in

Actel's Designer software. The functionality of TDI, TCK,

and TDO pins is controlled by the BST TAP controller. The

TAP controller receives two control inputs, TMS and TCK.

Upon power-up, the TAP controller enters the Test-Logic-

Reset state. In this state, TDI, TCK, and TDO function as

user I/Os. The TDI, TCK, and TDO pins are transformed

from user I/Os into BST pins when the TMS pin is LOW at

the first rising edge of TCK. The TDI, TCK, and TDO pins

return to user I/Os when TMS is held HIGH for at least

five TCK cycles.

Table 1-5

describes

the

different

configuration

requirements of BST pins and their functionality in

different modes.

TRST Pin

The TRST pin functions as a dedicated Boundary-Scan

Reset pin when the "Reserve JTAG Test Reset" option is

selected as shown in Figure 1-12. An internal pull-up

resistor is permanently enabled on the TRST pin in this

mode. It is recommended to connect this pin to GND in

normal operation to keep the JTAG state controller in

the Test-Logic-Reset state. When JTAG is being used, it

can be left floating or be driven HIGH.

When the "Reserve JTAG Test Reset" option is not

selected, this pin will function as a regular I/O. If unused

as an I/O in the design, it will be configured as a tristated

output.

Table 1-4 • Boundary Scan Pin Functionality

Dedicated Test Mode

Flexible Mode

TCK, TDI, TDO are dedicated

BST pins

TCK, TDI, TDO are flexible and

may be used as I/Os

No need for pull-up resistor for

TMS and TDI

Use a pull-up resistor of 10 k

Ω

on TMS

Figure 1-12 • Device Selection Wizard

Table 1-5 • Boundary-Scan Pin Configurations and

Functions

Mode

Designer

"Reserve JTAG"

Selection

TAP Controller

State

Dedicated (JTAG)

Checked

Any

Flexible (User I/O)

Unchecked

Test-Logic-Reset

Flexible (JTAG)

Unchecked

Any EXCEPT Test-

Logic-Reset

EX128-CS100 Datasheet(PDF) 13 Page - Actel Corporation

EX128-CS100 Datasheet(HTML) 13 Page - Actel Corporation

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