A32100DX-FPLC datasheet(34/84 Pages) ACTEL

34 / 84 page

Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s

Discontinued – v3.0

A326 5DX Timing Char acte r ist i cs

(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)

‘–3’ Speed

‘–2’ Speed

‘–1’ Speed

‘Std’ Speed

‘–F’ Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

Logic ModulePropagation Delays1

Combinatorial Functions

tPD

Internal Array Module Delay

2.1

2.4

2.9

3.7

3.2

tPDD

Internal Decode Module Delay

2.5

2.8

3.4

4.4

3.7

Predicted Routing Delays2

tRD1

FO=1 Routing Delay

0.3

0.4

0.5

0.6

0.5

tRD2

FO=2 Routing Delay

0.7

0.8

0.9

1.2

1.0

tRD3

FO=3 Routing Delay

1.0

1.2

1.4

1.8

1.6

tRD4

FO=4 Routing Delay

1.4

1.6

1.9

2.4

2.1

tRD5

FO=8 Routing Delay

2.7

3.2

3.7

4.9

4.1

tRDD

Decode-to-Output Routing Delay

0.46

0.5

0.62

0.8

0.7

Sequential Timing Characteristics3, 4

tCO

Flip-Flop Clock-to-Output

2.3

2.7

3.1

4.1

3.5

tGO

Latch Gate-to-Output

2.1

2.4

2.9

3.7

3.2

tSUD

Flip-Flop (Latch) Set-Up Time

0.35

0.4

0.47

0.6

0.5

tHD

Flip-Flop (Latch) Hold Time

0.0

tRO

Flip-Flop (Latch) Reset to Output

2.3

2.7

3.1

4.1

3.5

tSUENA

Flip-Flop (Latch) Enable Set-Up

0.75

0.9

1.0

1.3

1.1

tHENA

Flip-Flop (Latch) Enable Hold

0.0

tWCLKA

Flip-Flop (Latch) Clock Active Pulse Width

3.7

4.2

4.9

6.4

5.5

tWASYN

Flip-Flop (Latch) Asynchronous Pulse Width

4.9

5.5

6.5

8.4

7.1

Notes:

For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.

Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device

performance. Post-route timing analysis or simulation is required to determine actual performance.

Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from

the DirectTime Analyzer utility.

Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing

parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts

(adds) to the internal set-up (hold) time.

VCC = 3.0V for 3.3V specifications.

A32100DX-FPLC Datasheet(PDF) 34 Page - Actel Corporation

A32100DX-FPLC Datasheet(HTML) 34 Page - Actel Corporation

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