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A32100DX-FPLC Datasheet(PDF) 40 Page - Actel Corporation

Part # A32100DX-FPLC
Description  Integrator Series FPGAs: 1200XL and 3200DX Families
PDF  84 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

A32100DX-FPLC Datasheet(HTML) 40 Page - Actel Corporation

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Inte gra t or Serie s FP GAs: 1 200XL a nd 3200 DX F amilie s
40
Discontinued – v3.0
A321 00DX Timing Char act eristics
(Worst-Case Commercial Conditions VCC = 4.75 V, TJ = 70°C)
‘–3 Speed
‘–2 Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
3.3V ‘Std’
Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic ModulePropagation Delays
Combinatorial Functions
tPD
Internal Array Module Delay
2.2
2.6
3.0
3.5
5.2
4.1
ns
tPDD
Internal Decode Module Delay
2.4
2.7
3.1
3.7
5.7
4.3
ns
Predicted Module Routing Delays
tRD1
FO=1 Routing Delay
1.0
1.1
1.3
1.5
3.3
1.7
ns
tRD2
FO=2 Routing Delay
1.4
1.7
1.9
2.2
4.3
2.5
ns
tRD3
FO=3 Routing Delay
1.8
2.1
2.5
2.9
5.2
3.4
ns
tRD4
FO=4 Routing Delay
2.4
2.7
3.1
3.7
6.5
4.3
ns
tRD5
FO=8 Routing Delay
4.2
5.0
5.6
6.6
10.0
7.7
ns
tRDD
Decode-to-Output Routing Delay
0.3
0.37
0.4
0.5
0.4
0.6
ns
Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
2.2
2.6
3.0
3.5
5.0
4.1
ns
tGO
Latch Gate-to-Output
2.2
2.6
3.0
3.5
5.0
4.1
ns
tSU
Flip-Flop (Latch) Set-Up Time
0.3
0.37
0.4
0.5
0.7
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
2.2
2.6
3.0
3.5
5.0
4.1
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.75
0.9
1.0
1.4
0.85
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
3.1
3.7
4.2
4.9
7.0
5.7
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
4.1
4.8
5.4
6.4
7.0
7.5
ns



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