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LTC1699 Series

pin is used to shut down the converters without the need

for lengthy SMBus Off protocols and can also be used to

turn on up to three DC/DC converters simultaneously. The

VRON pin has an internal 2.5uA current source pull-up.

The CPU_ON, IO_ON and CLK_ON pins are N-channel,

open drain outputs. These outputs can be connected to the

RUN/SS pin of LTC DC/DC converters that generate the

VCC supplies of the CPU, I/O circuits and the clock buffer.

The RUN/SS pin shuts down the converter if pulled low

and also serves as a connection for the soft-start capaci-

tor. The CPU_ON, IO_ON and CLK_ON pins are open drain

outputs and do not interfere with soft-start when switched

into a high impedance state. To keep the I/O and clock

buffer VCC supplies alive at all times, disconnect the IO_ON

and CLK_ON pins from the corresponding RUN/SS pins.

The N-channel FETs at the CPU_ON, IO_ON and CLK_ON

pins typically discharge a 0.1

µF(0.01µF)soft-startcapaci-

tor from 3V to 0.35V in 21

µs (2.3µs) with VCC = 2.7V.

The PGOOD or “Power Good” pin is also an open drain,

N-channel output. The PGOOD pin pulls low if the DC/DC

converters are shutdown. If the converters are turned on,

an internal timer keeps PGOOD low for 50

µs (typical)

which allows time for the converters to enter regulation.

Toggling the SEL pin while the converters are turned on

also causes the PGOOD pin to pull low for 50

µs. The

PGOOD pin may be used to force continuous operation in

an LTC DC/DC converter. If the SEL pin is toggled to select

a lower output voltage, it may take an unacceptably long

time for the output of the DC/DC converter to decrease to

the new voltage under light load conditions. To reduce this

time needed, the PGOOD pin can be connected to the FCB

(force continuous bar) pin of the converter. When the SEL

pin is toggled to select a new code, FCB pin is forced low

for 50

µs. This forces the DC/DC converter out of Burst

Mode

TM operation and into continuous mode.

The VRON pin and SMBON, the output of the internal on/

off state machine, control the state of the CPU_ON, IO_ON,

CLK_ON and PGOOD pins. The DCON signal is a logical

NAND function of the logical states of VRON and SMBON

and is the status bit that is returned during Read-back.

Table 3 shows the state of the CPU_ON, IO_ON, and

CLK_ON pins for various combinations of VRON and

SMBON.

Table 3. DC/DC Converter Control Pins

VRON

SMBON

DCON

PGOOD

CPU_ON, IO_ON, CLK_ON

(Note 3)

↑↓

0 for 50

µs

Z (Note 2)

(Note 1)

↑

↓

0 for 50

µs

Z (Note 2)

(Note 1)

Note 1: Also triggered by SEL pin toggling.

Note 2: Z = High Impedance

Note 3: X = Don’t care

If the DCON control bit goes high, the N-channel transistor

at the CPU_ON, IO_ON, CLK_ON and PGOOD pins turn on,

pulling these pins to ground. Any connected RUN/SS pins

are pulled to ground, shutting down the converters.

If the DCON control bit goes low, the N-channel transistor

at the CPU_ON, CLK_ON, IO_ON and PGOOD pins turn off

and become high impedance outputs. This allows the soft-

start capacitor at each RUN/SS pin to charge up and the

DC/DC converters wake up gradually with a soft-start

cycle. The PGOOD pin also pulls low for typically 50

µs to

indicate that the converter outputs are temporarily out of

regulation. An internal timer determines the duration of

the low pulse. The timer is triggered by SEL toggling or

DCON going low.

Power-Up Reset

On power-up, the internal POR circuit generates a low

reset pulse, which stays low until VCC rises above approxi-

mately 2.2V. The reset pulse forces the SMBus interface

into an idle state in which it listens for a start bit. At the

same time the outputs of both Register 0 and Register 1

are set to 11111B. The DCON bit is pulled high so that the

CPU_ON, IO_ON, CLK_ON and PGOOD pins are pulled low

to shut down the DC/DC converters.

APPLICATIO S I FOR ATIO

Burst Mode is a trademark of Linear Technology Corporation.

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