80C52 datasheet(6/54 Pages) TEMIC

6 / 54 page

Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

MNEMONIC

PIN NUMBER

TYPE

NAME AND FUNCTION

ALE/PROG

O (I)

Address Latch Enable/Program Pulse: Output pulse for latching the low byte

of the address during an access to external memory. In normal operation, ALE

is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one ALE pulse is

skipped during each access to external data memory. This pin is also the program

pulse input (PROG) during EPROM programming. ALE can be disabled by

setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal

fetches.

PSEN

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

EA/VPP

External Access Enable/Programming Supply Voltage: EA must be externally

held low to enable the device to fetch code from external program memory

locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is

held high, the device executes from internal program memory unless the program

counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must

be held low for ROMless devices. This pin also receives the 12.75V programming

supply voltage (VPP) during EPROM programming. If security level 1 is

programmed, EA will be internally latched on Reset.

XTAL1

Crystal 1: Input to the inverting oscillator ampliﬁer and input to the internal

clock generator circuits.

XTAL2

Crystal 2: Output from the inverting oscillator ampliﬁer

Table 3. Pin Description for 40/44 pin packages

80C52 Datasheet(PDF) 6 Page - TEMIC Semiconductors