80C52 datasheet(7/54 Pages) TEMIC

7 / 54 page

Rev. B - Jan. 25, 1999

Preliminary

TS80C52X2

6. TS80C52X2 Enhanced Features

In comparison to the original 80C52, the TS80C52X2 implements some new features, which are:

• The X2 option.

• The Dual Data Pointer.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mode.

• The ALE disabling.

• Some enhanced features are also located in the UART and the timer 2.

6.1 X2 Feature

The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following

advantages:

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Save power consumption while keeping same CPU power (oscillator power saving).

Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main

clock input of the core (phase generator). This divider may be disabled by software.

6.1.1 Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and

peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,

the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block

diagram. X2 bit is validated on XTAL1

÷2 rising edge to avoid glitches when switching from X2 to STD mode.

Figure 2. shows the mode switching waveforms.

Figure 1. Clock Generation Diagram

XTAL1

CKCON reg

state machine: 6 clock cycles.

CPU control

FOSC

FXTAL

XTAL1:2

80C52 Datasheet(PDF) 7 Page - TEMIC Semiconductors