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LTM9001

9001fa

INPUT SPAN

The LTM9001 is conﬁgured with a ﬁxed input span and

input impedance. With the ampliﬁer gain and the ADC input

network described above for LTM9001-AA, the full-scale

input range of the driver circuit is 250mVP-P. The recom-

mended ADC input span is achieved by tying the SENSE

pin to VDD. However, the ADC input span can be changed

by applying a DC voltage to the SENSE pin.

Input Impedance and Matching

The differential input impedance of the LTM9001 can be

50Ω, 200Ω or 400Ω. In some applications the differential

inputs may need to be terminated to a lower value imped-

ance, e.g. 50Ω, in order to provide an impedance match

for the source. Several choices are available.

One approach is to use a differential shunt resistor

(Figure 2). Another approach is to employ a wide band

transformer (Figure 3). Both methods provide a wide band

match. The termination resistor or the transformer must

be placed close to the input pins in order to minimize the

reﬂection due to input mismatch.

Table 2. Differential Ampliﬁer Input Termination Values

ZIN

RT FIG 2

400Ω

57Ω

200Ω

66.5Ω

50Ω

None

9001 F02

ZIN/2

LTM9001

ZIN/2

25Ω

VIN

IN+

IN–

–

9001 F03

ZIN/2

LTM9001

ZIN/2

25Ω

VIN

–

•

IN+

IN–

Figure 2. Input Termination for Differential 50Ω Input Impedance

Using Shunt Resistor (See Table 2 for RT Values)

Figure 3. Input Termination for Differential 50Ω

Input Impedance Using a Wideband Transformer

OPERATION

ADC INPUT NETWORK

The passive network between the ampliﬁer output stage

and the ADC input stage can be conﬁgured for bandpass

or low-pass response with different cut-off frequencies

and bandwidths. The LTM9001-AA, for example, imple-

ments a 2-pole band-pass ﬁlter centered at 162.5MHz

with 50MHz bandwidth. Note that the ﬁlter attenuates the

signal at 162.5MHz by 1dB, making the overall gain of the

subsystem 19dB.

For production test purposes the ﬁlter is designed to allow

DC inputs into the ADC.

CONVERTER INFORMATION

The analog-to-digital converter (ADC) is a CMOS pipelined

multistep converter with a front-end PGA. As shown in the

Functional Block Diagram, the converter has ﬁve pipelined

ADC stages; a sampled analog input will result in a digitized

value seven cycles later (see the Timing Diagram section).

The encode input is differential for improved common

mode noise immunity.

APPLICATIONS INFORMATION

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