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LTC4258 Datasheet(PDF) 4 Page - Linear Technology |
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LTC4258 Datasheet(HTML) 4 Page - Linear Technology |
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4 / 28 page ![]() LTC4258 4 4258fb ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND = DGND = 0V, VDD = 3.3V, VEE = –48V unless otherwise noted (Note 5). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSTART Maximum Current Limit Duration During tSTART1 = 0, tSTART0 = 0 (Figure 3) ● 50 60 70 ms Port Start-Up tSTART1 = 0, tSTART0 = 1 (Figure 3) ● 25 30 35 ms tSTART1 = 1, tSTART0 = 0 (Figure 3) ● 100 120 140 ms tSTART1 = 1, tSTART0 = 1 (Figure 3) ● 200 240 280 ms tICUT Maximum Current Limit Duration After tICUT1 = 0, tICUT0 = 0 (Figure 3) ● 50 60 70 ms Port Start-Up tICUT1 = 0, tICUT0 = 1 (Figure 3) ● 25 30 35 ms tICUT1 = 1, tICUT0 = 0 (Figure 3) ● 100 120 140 ms tICUT1 = 1, tICUT0 = 1 (Figure 3) ● 200 240 280 ms DCCLMAX Maximum Current Limit Duty Cycle Reg16h = 00h ● 5.8 6.3 6.7 % tDIS Disconnect Delay tDIS1 = 0, tDIS0 = 0 (Figure 4) ● 300 360 400 ms tDIS1 = 0, tDIS0 = 1 (Figure 4) ● 75 90 100 ms tDIS1 = 1, tDIS0 = 0 (Figure 4) ● 150 180 200 ms tDIS1 = 1, tDIS0 = 1 (Figure 4) ● 600 720 800 ms tVMIN DC Disconnect Minimum Pulse VSENSEn – VEE > 5mV, VOUTn = –48V (Figure 4) ● 0.02 1 ms Width Sensitivity (Note 9) I2C Timing fSCLK Clock Frequency (Note 9) ● 400 kHz t1 Bus Free Time Figure 5 (Notes 9, 10) ● 1.3 µs t2 Start Hold Time Figure 5 (Notes 9, 10) ● 600 ns t3 SCL Low Time Figure 5 (Notes 9, 10) ● 1.3 µs t4 SCL High Time Figure 5 (Notes 9, 10) ● 600 ns t5 Data Hold Time Figure 5 (Notes 9, 10) ● 150 ns t6 Data Set-Up Time Figure 5 (Notes 9, 10) ● 200 ns t7 Start Set-Up Time Figure 5 (Notes 9, 10) ● 600 ns t8 Stop Set-Up Time Figure 5 (Notes 9, 10) ● 600 ns tr SCL, SDAIN Rise Time Figure 5 (Notes 9, 10) ● 20 300 ns tf SCL, SDAIN Fall Time Figure 5 (Notes 9, 10) ● 20 150 ns tFLTINT Fault Present to INT Pin Low (Notes 9, 10, 11) ● 20 150 ns tSTOPINT Stop Condition to INT Pin Low (Notes 9, 10, 11) ● 60 200 ns tARAINT ARA to INT Pin High Time (Notes 9, 10) ● 20 300 ns pins are negative. All voltages are referenced to ground (AGND and DGND) unless otherwise specified. Note 6: The LTC4258 is designed to maintain a port voltage of –46.6V to –57V. The VEE supply voltage range accounts for the drop across the MOSFET and sense resistor. Note 7: The LTC4258 implements overload current detection per IEEE 802.3af. The minimum overload current (ICUT) is dependent on port voltage; ICUT_MIN = 15.4W/VPORT_MIN. An IEEE compliant system using the LTC4258 should maintain port voltage above –46.6V. Note 8: VEE supply current while classifying a short is measured indirectly by measuring the DETECT n pin current while classifying a short. Note 9: Guaranteed by design, not subject to test. Note 10: Values measured at VILD and VIHD. Note 11: If fault occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: DGND and AGND should be tied together in normal operation. Note 3: An internal clamp limits the GATE pins to a minimum of 12V above VEE. Driving this pin beyond the clamp may damage the part. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125 °C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: All currents into device pins are positive; all currents out of device |
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