LTC1771 datasheet(6/16 Pages) LINER

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LTC1771

(Refer to Functional Block Diagram)

Main Control Loop

The LTC1771 uses a constant off-time, current mode

step-down architecture. During normal operation, the

P-channel MOSFET is turned on at the beginning of each

cycle and turned off when the current comparator C

triggers the 1-shot timer. The external MOSFET switch

stays off for the 3.5

µs 1-shot duration and then turns back

on again to begin a new cycle. The peak inductor current

at which C triggers the 1-shot is controlled by the voltage

on Pin 3 (ITH), the output of the error amplifier EA. An

external resistive divider connected between VOUT and

ground allows EA to receive an output feedback voltage

VFB. When the load current increases, it causes a slight

decrease in VFB relative to the 1.23V reference, which in

turn causes the ITH voltage to increase until the average

inductor current matches the new load current.

The main control loop is shut down by pulling Pin 1

(RUN/SS) low. Releasing RUN/SS allows an internal 1

µA

current source to charge soft-start capacitor CSS. When

CSS reaches 1V, the main control loop is enabled with the

ITH voltage clamped at approximately 40% of its maxi-

mum value. As CSS continues to charge, ITH is gradually

released allowing normal operation to resume.

Burst Mode Operation

The LTC1771 provides outstanding low current efficiency

and ultralow no-load supply current by using Burst Mode

operation when the MODE pin is pulled above 2V. During

Burst Mode operation, short burst cycles of normal switch-

ing are followed by a longer idle period with the switch off

and the load current is supplied by the output capacitor.

During this idle period, only the minimum required cir-

cuitry—1.23V reference and error amp—are left on, and

the supply current is reduced to 9

µA.Atnoload,theoutput

capacitor is still discharged very slowly by leakage current

in the Schottky diode and feedback resistor current result-

ing in very low frequency burst cycles that add a few more

microamps to the supply current.

Burst Mode operation is provided by clamping the mini-

mum ITH voltage at 1V which represents about 25% of

maximum load current. If the load falls below this level, i.e.

the ITH voltage tries to fall below 1V, the burst comparator

B switches state signaling the LTC1771 to enter sleep

mode. During this time, EA is reduced to 10% of its normal

operating current and the external compensation capaci-

tor is disconnected and clamped to 1V so that the EA can

drive its output with the lower available current. As the load

discharges the output capacitor, the internal ITH voltage

increases. When it exceeds 1V the burst comparator exits

sleep mode, reconnects the external compensation com-

ponents to the error amplifier output, and returns EA to full

power along with the other necessary circuitry. This

scheme (patent pending) allows the EA to be reduced to

such a low operating current during sleep mode without

adding unacceptable delay to wake up the LTC1771 due to

the compensation capacitor on ITH required for stability in

normal operation.

Burst Mode operation can be disabled by pulling the

MODE pin to ground. In this mode of operation, the burst

comparator B is disabled and the ITH voltage allowed to go

all the way to 0V. The load can now be reduced to about 1%

of maximum load before the loop skips cycles to maintain

regulation. This mode provides a low noise output spec-

trum, useful for reducing both audio and RF interference,

at the expense of reduced efficiency at light loads.

Off-Time

The off-time duration is 3.5

µs when the feedback voltage

is close to the reference voltage; however, as the feedback

voltage drops, the off-time lengthens and reaches a maxi-

mum value of about 70

µs when VFB is zero. This ensures

that the inductor current has enough time to decay when

the reverse voltage across the inductor is low such as

during short circuit, thus protecting the MOSFET and

inductor.

OPERATIO

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