LTM4616 datasheet(7/24 Pages) LINER

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LTM4616

4616fa

PIN FUNCTIONS

PolyPhase is a registered trademark of Linear Technology Corporation.

MODE1 and MODE2 (A8 and G8): Mode Select Input for

Each Channel. Tying this pin high enables Burst Mode

operation. Tying this pin low enables forced continuous

operation. Floating this pin or tying it to VIN/2 enables

pulse-skipping operation.

CLKIN1 and CLKIN2 (A7 and G7): External Synchronization

Input to Phase Detector for Each Channel. This pin is

internally terminated to SGND with a 50k resistor. The

phase-locked loop will force the internal top power PMOS

turn on to be synchronized with the rising edge of the

CLKIN signal. Connect this pin to SVIN to enable spread

spectrum modulation. During external synchronization,

make sure the PLLLPF pin is not tied to VIN or GND.

PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop

Lowpass Filter for Each Channel. An internal lowpass ﬁlter

is tied to this pin. In spread spectrum mode, placing a

capacitor here to SGND controls the slew rate from one

frequency to the next. Alternatively, ﬂoating this pin allows

normal running frequency at 1.5MHz, tying this pin to SVIN

forces the part to run at 1.33 times its normal frequency

(2MHz), tying it to ground forces the frequency to run at

0.67 times its normal frequency (1MHz).

PHMODE1 and PHMODE2 (A9 and G9): Phase Selector

Input for Each Channel. This pin determines the phase

relationship between the internal oscillator and CLKOUT. Tie

it high for 2-phase operation, tie it low for 3-phase operation,

and ﬂoat or tie it to VIN/2 for 4-phase operation.

MGN1 and MGN2 (A10 and G10): Voltage Margining Pin

for Each Channel. Tie this pin to VOUT to disable margining.

For margining, connect a voltage divider from VIN to GND

with the center point connected to the MGN pin for the

speciﬁc channel. Each resistor should be close to 50k.

Margin High is within 0.3V of VIN, and Margin Low is

within 0.3V of GND. See the Applications section and

Figure 18 for margining control. The speciﬁed tri-state

drivers are capable of the high and low requirements for

margining.

BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin

for Each Channel. Tying BSEL low selects ±5% margin

value, tying it high selects 10% margin value. Floating it

or tying it to VIN/2 selects 15% margin value.

TRACK1 and TRACK2 (E8 and L8): Output Voltage Tracking

Pin for Each Channel. Voltage tracking is enabled when

the TRACK voltage is below 0.57V. If tracking is not

desired, then connect the TRACK pin to SVIN. If TRACK

is not tied to SVIN, then the TRACK pin’s voltage needs to

be below 0.18V before the chip shuts down even though

RUN is already low. Do not ﬂoat this pin. A resistor and

capacitor can be applied to the TRACK pin to increase the

soft-start time of the regulator. TRACK1 and TRACK2 can

be tied together for parallel operation and tracking. See

the Applications section.

FB1 and FB2 (D8 and K8): The Negative Input of the Error

Ampliﬁer for Each Channel. Internally, this pin is connected

to VOUT with a 10k precision resistor. Different output

voltages can be programmed with an additional resistor

between FB and GND pins. In PolyPhase

® operation, tying

the FB pins together allows for parallel operation. See

Applications section for details.

ITH1 and ITH2 (F8 and M8): Current Control Threshold and

Error Ampliﬁer Compensation Point for Each Channel. The

current comparator threshold increases with this control

voltage. Tie together in parallel operation.

ITHM1 and ITHM2(E7 and L7): Negative Input to the Internal

ITH Differential Ampliﬁer for Each Channel. Tie this pin to

SGND for single phase operation on each channel. For

PolyPhase operation, tie the master’s ITHM to SGND while

connecting all of the ITHM pins together at the master.

PGOOD1 and PGOOD2 (A11 and G11): Output Voltage

Power Good Indicator for Each Channel. Open-drain logic

output that is pulled to ground when the output voltage

is not within ±10% of the regulation point. Power good

is disabled during margining.

RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage

above 1.5V will turn on the module.

SW1 and SW2 (B6 and H6): Switching Node of Each

Channel That is Used for Testing Purposes. This can be

connected to copper on the board for improved thermal

performance.

CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock

Signal for PolyPhase Operation. The phase of CLKOUT is

determined by the state of the PHMODE pin.

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