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LTC1929/LTC1929-PG

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

The term (1 +

δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs. Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. CRSS is usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

The Schottky diodes, D1 and D2 shown in Figure 1 conduct

during the dead-time between the conduction of the two

large power MOSFETs. This helps prevent the body diode

of the bottom MOSFET from turning on, storing charge

during the dead-time, and requiring a reverse recovery

period which would reduce efficiency. A 1A to 3A (depend-

ing on output current) Schottky diode is generally a good

compromise for both regions of operation due to the

relatively small average current. Larger diodes result in

additional transition losses due to their larger junction

capacitance.

CIN and COUT Selection

In continuous mode, the source current of each top

N-channel MOSFET is a square wave of duty cycle VOUT/

VIN. A low ESR input capacitor sized for the maximum

RMS current must be used. The details of a close form

equation can be found in Application Note 77. Figure 4

shows the input capacitor ripple current for a 2-phase

configuration with the output voltage fixed and input

voltage varied. The input ripple current is normalized

against the DC output current. The graph can be used in

place of tedious calculations. The minimum input ripple

current can be achieved when the input voltage is twice the

output voltage. The minimum is not quite zero due to

inductor ripple current.

In the graph of Figure 4, the local maximum input RMS

capacitor currents are reached when:

OUT

−

where k = 1, 2.

These worst-case conditions are commonly used for de-

sign because even significant deviations do not offer much

relief. Note that capacitor manufacturer’s ripple current

ratings are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor, or to

choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to meet

size or height requirements in the design. Always consult

the capacitor manufacturer if there is any question.

It is important to note that the efficiency loss is propor-

tional to the input RMS current

squared and therefore a

2-stage implementation results in 75% less power loss

when compared to a single phase design. Battery/input

protection fuse resistance (if used), PC board trace and

connector resistance losses are also reduced by the re-

duction of the input ripple current in a 2-phase system. The

required amount of input capacitance is further reduced by

the factor, 2, due to the effective increase in the frequency

of the current pulses.

The selection of COUT is driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment has been met, the RMS current rating generally far

exceeds the IRIPPLE(P-P) requirements. The steady state

output ripple (

∆VOUT) is determined by:

∆∆

ESR

OUT

RIPPLE

OUT

≈+









APPLICATIO S I FOR ATIO

Figure 4. Normalized RMS Input Ripple Current

vs Duty Factor for 1 and 2 Output Stages

DUTY FACTOR (VOUT/VIN)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.6

0.5

0.4

0.3

0.2

0.1

1929 F04

2-PHASE

1-PHASE

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