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LTC1929/LTC1929-PG

after CSS reaches 4.1V, CSS begins discharging on the

assumption that the output is in an overcurrent condition.

If the condition lasts for a long enough period as deter-

mined by the size of CSS, the controller will be shut down

until the RUN/SS pin voltage is recycled. If the overload

occurs during start-up, the time can be approximated by:

tLO1 ≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS)

If the overload occurs after start-up the voltage on the

RUN/SS capacitor will continue charging and will provide

additional time before latching off:

tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor, RSS, to the RUN/SS pin as

shown in Figure 6. This resistance shortens the soft-start

period and prevents the discharge of the RUN/SS capaci-

tor during a severe overcurrent and/or short-circuit con-

dition. When deriving the 5

µA current from VIN as in the

figure, current latchoff is always defeated. The diode

connecting of this pull-up resistor to INTVCC, as in

Figure 6, eliminates any extra supply current during shut-

down while eliminating the INTVCC loading from prevent-

ing controller start-up.

Why should you defeat current latchoff? During the

prototyping stage of a design, there may be a problem with

noise pickup or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. A decision can be made after the design is com-

plete whether to rely solely on foldback current limiting or

to enable the latchoff feature by removing the pull-up

resistor.

APPLICATIO S I FOR ATIO

Figure 6. RUN/SS Pin Interfacing

The value of the soft-start capacitor CSS may need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

CSS > (COUT )(VOUT)(10-4)(RSENSE)

The minimum recommended soft-start capacitor of CSS =

0.1

µF will be sufficient for most applications.

Phase-Locked Loop and Frequency Synchronization

The LTC1929 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is

±50% around the

center frequency fO. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

220kHz. The nominal operating frequency range of the

LTC1929 is 140kHz to 310kHz.

The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range,

∆fH, is equal to the capture range, ∆fC:

∆fH = ∆fC = ±0.5 fO (150kHz-300kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin. A simplified block

diagram is shown in Figure 7.

EXTERNAL

OSC

2.4V

RLP

10k

CLP

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PHASE

DETECTOR

PLLIN

1929 F07

PLLFLTR

50k

Figure 7. Phase-Locked Loop Block Diagram

3.3V OR 5V

RUN/SS

VIN

INTVCC

RUN/SS

D1*

CSS

RSS*

CSS

RSS*

1929 F06

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

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