LTC2274 datasheet(18/40 Pages) LINER

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LTC2274

2274f

APPLICATIONS INFORMATION

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2274 CMOS

differential sample and hold. The differential analog inputs

are sampled directly onto sampling capacitors (CSAMPLE)

through NMOS transistors. The capacitors shown attached

to each input (CPARASITIC) are the summation of all other

capacitance associated with each input.

During the sample phase when ENC is low, the NMOS

transistors connect the analog inputs to the sampling

capacitors and they charge to, and track, the differential

input voltage. On the rising edge of ENC, the sampled

input voltage is held on the sampling capacitors. During

the hold phase when ENC is high, the sampling capacitors

are disconnected from the input and the held voltage is

passed to the ADC core for processing. As ENC transitions

for high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitors still hold the previous sample, a charging glitch

proportional to the change in voltage between samples will

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such

as the change seen with input frequencies near Nyquist,

then a larger charging glitch will be seen.

Common Mode Bias

The ADC sample-and-hold circuit requires differential drive

to achieve speciﬁed performance. Each input should swing

±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for

the 1.5V range (PGA = 1), around a common mode volt-

age of 1.25V. The VCM output pin (Pin 39) is designed to

provide the common mode bias level. VCM can be tied

directly to the center tap of a transformer to set the DC

input level or as a reference level to an op amp differential

driver circuit. The VCM pin must be bypassed to ground

close to the ADC with 2.2μF or greater.

Input Drive Impedance

As with all high performance, high speed ADCs the dy-

namic performance of the LTC2274 can be inﬂuenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reactance

can inﬂuence SFDR. At the falling edge of ENC the

sample-and-hold circuit will connect the 4.9pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when ENC rises, holding the

sampled input on the sampling capacitor. Ideally, the

input circuitry should be fast enough to fully charge

the sampling capacitor during the sampling period

1/(2FENCODE); however, this is not always possible and the

incomplete settling may degrade the SFDR. The sampling

glitch has been designed to be as linear as possible to

minimize the effects of incomplete settling.

For the best performance it is recommended to have a

source impedance of 100

Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

CSAMPLE

4.9pF

VDD

LTC2274

AIN+

2274 F02

CSAMPLE

4.9pF

VDD

AIN–

ENC–

ENC+

1.6V

CPARASITIC

1.8pF

CPARASITIC

1.8pF

RPARASITIC

3Ω

RON

20Ω

RON

20Ω

RPARASITIC

3Ω

Figure 2. Equivalent Input Circuit

LTC2274 Datasheet(PDF) 18 Page - Linear Technology

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