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LTC2446 Datasheet(PDF) 18 Page - Linear Technology |
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LTC2446 Datasheet(HTML) 18 Page - Linear Technology |
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18 / 28 page ![]() LTC2446/LTC2447 18 24467fa Internal Serial Clock, Single Cycle Operation This timing mode uses an internal serial clock to shift out the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 7. In order to select the internal serial clock timing mode, the EXT pin must be tied HIGH. The serial data output pin (SDO) is Hi-Z as long as CS is HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. Once CS is pulled LOW, SCK goes LOW and EOC is output to the SDO pin. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Alternatively, BUSY (Pin 2) may be used to monitor the status of the conversion in progress. BUSY is HIGH during the conver- Figure 7. Internal Serial Clock, Single Cycle Operation sion and goes LOW at the conclusion. It remains LOW until the result is read from the device. When testing EOC, if the conversion is complete (EOC = 0), the device will exit the sleep state and enter the data output state if CS remains LOW. In order to prevent the device from exiting the low power sleep state, CS must be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins outputting data at time tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW during the falling edge of EOC). The value of tEOCtest is 500ns. If CS is pulled HIGH before time tEOCtest, the device remains in the sleep state. The conversion result is held in the internal static shift register. APPLICATIO S I FOR ATIO MSB BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 0 LSB Hi-Z 244676 F07 SIG BIT 29 “0” BIT 30 EOC Hi-Z CS SCK SDI SDO BUSY BIT 31 1 0 EN SGL GLBL A1 A0 OSR3 OSR2 OSR1 OSR0 TWOX ODD 12345 6 7 89 10 11 12 13 14 32 CONVERSION SLEEP DATA OUTPUT CONVERSION TEST EOC TEST EOC DON'T CARE DON'T CARE <tEOC(TEST) VCC FO REF67+ REF67– CH0 CH1 CH2 CH7 COM REFG+ REFG– REF01+ REF01– SCK SDI SDO CS GND 28 29 30 11 10 35 24 23 8 9 12 22 7 38 37 1,4,5,6,31,32,33 36 34 USER SELECTABLE REFERENCES 0.1V TO VCC ANALOG INPUTS ... ... 2 = EXTERNAL OSCILLATOR = INTERNAL OSCILLATOR 1 µF 4.5V TO 5.5V LTC2446 4-WIRE SPI INTERFACE BUSY |
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