LTC2482 datasheet(13/32 Pages) LINER

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LTC2482

2482fb

APPLICATIONS INFORMATION

Bit 23 (ﬁrst output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is low.

This bit is high during the conversion and goes low when

the conversion is complete.

Bit 22 (second output bit) is a dummy bit (DMY) and is

always low.

Bit 21 (third output bit) is the conversion result sign

indicator (SIG). If VIN is >0, this bit is high. If VIN is <0,

this bit is low.

Bit 20 (fourth output bit) is the most signiﬁcant bit (MSB)

of the result. This bit in conjunction with Bit 21 also

provides the underrange or overrange indication. If both

Bit 21 and Bit 20 are high, the differential input voltage is

above +FS. If both Bit 21 and Bit 20 are low, the differential

input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2482 Status Bits

INPUT RANGE

BIT 23

EOC

BIT 22

DMY

BIT 21

SIG

BIT 20

MSB

VIN ≥ 0.5 • VREF

0011

0V ≤ VIN < 0.5 • VREF

0010

–0.5 • VREF ≤ VIN < 0V

0001

VIN < –0.5 • VREF

0000

Bits 20-4 are the 16-bit plus sign conversion result MSB

ﬁrst.

Bits 3-0 are always low and are included to maintain

software compatibility with the LTC2480.

Data is shifted out of the SDO pin under control of the

serial clock (SCK) (see Figure 2). Whenever CS is high,

SDO remains high impedance and any externally gener-

ated SCK clock pulses are ignored by the internal data

out shift register.

In order to shift the conversion result out of the device,

CS must ﬁrst be driven low. EOC is seen at the SDO pin

of the device once CS is pulled low. EOC changes in real

time from high to low at the completion of a conversion.

This signal may be used as an interrupt for an external

microcontroller. Bit 23 (EOC) can be captured on the ﬁrst

rising edge of SCK. Bit 22 is shifted out of the device on

the ﬁrst falling edge of SCK. The ﬁnal data bit (Bit 0) is

shifted out on the falling edge of the 23rd SCK and may

be latched on the rising edge of the 24th SCK pulse. On

the falling edge of the 24th SCK pulse, SDO goes high

indicating the initiation of a new conversion cycle. This

bit serves as EOC (Bit 23) for the next conversion cycle.

Table 2 summarizes the output data format.

As long as the voltage on the IN+ and IN– pins is main-

tained within the –0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater

than +FS, the conversion result is clamped to the value

corresponding to the +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value corresponding to –FS – 1LSB.

Table 2. LTC2482 Output Data Format

DIFFERENTIAL INPUT VOLTAGE

VIN*

BIT 23

EOC

BIT 22

DMY

BIT 21

SIG

BIT 20

MSB

BIT 19

BIT 18

BIT 17

…

BIT 4

BITS 3-0

VIN* ≥ FS**

0011000

…

FS** – 1LSB

0010111

…

0.5 • FS**

0010100

…

0.5 • FS** – 1LSB

0010011

…

0010000

…

–1LSB

0001111

…

–0.5 • FS**

0001100

…

–0.5 • FS** – 1LSB

0001011

…

–FS**

0001000

…

VIN* < –FS**

0000111

…

*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF.

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