LTC2492 datasheet(21/36 Pages) LINER

21 / 36 page

LTC2492

2492fb

External Serial Clock, Single Cycle Operation

This timing mode uses an external serial clock to shift out

the conversion result and CS to monitor and control the

state of the conversion cycle (see Figure 6).

The external serial clock mode is selected during the power-

up sequence and on each falling edge of CS. In order to

enter and remain in the external SCK mode of operation,

SCK must be driven LOW both at power up and on each

CS falling edge. If SCK is HIGH on the falling edge of CS,

the device will switch to the internal SCK mode.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the conversion is complete and the device is in the sleep

state. Independent of CS, the device automatically enters

the sleep state once the conversion is complete; however,

in order to reduce the power, CS must be HIGH.

When the device is in the sleep state, its conversion result

is held in an internal static shift register. The device remains

in the sleep state until the ﬁrst rising edge of SCK is seen

while CS is LOW. The input data is then shifted in via the

SDI pin on each rising edge of SCK (including the ﬁrst rising

edge). The channel selection and converter conﬁguration

mode will be used for the following conversion cycle. If

the input channel or converter conﬁguration is changed

during this I/O cycle, the new settings take effect on the

conversion cycle following the data input/output cycle.

The output data is shifted out the SDO pin on each falling

edge of SCK. This enables external circuitry to latch the

output on the rising edge of SCK. EOC can be latched on the

ﬁrst rising edge of SCK and the last bit of the conversion

result can be latched on the 32nd rising edge of SCK. On

the 32nd falling edge of SCK, the device begins a new

conversion and SDO goes HIGH (EOC = 1) indicating a

conversion is in progress.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

APPLICATIONS INFORMATION

Figure 6. External Serial Clock, Single Cycle Operation

Hi-Z

2492 F06

SCK

(EXTERNAL)

SDI

SDO

CONVERSION

SLEEP

DATA INPUT/OUTPUT

CONVERSION

VCC

REF+

REF–

CH0

CH1

CH2

CH3

COM

SCK

SDI

SDO

GND

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

LTC2492

2.7V TO 5.5V

0.1μF

10μF

4-WIRE

SPI INTERFACE

EOC

BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21

BIT 20 BIT 19

BIT 29

BIT 30

BIT 31

BIT 18 BIT 17

BIT 0

SGL

EN2

SPD

ODD

DON'T CARE

MSB

SIG

“0”

LTC2492 Datasheet(PDF) 21 Page - Linear Technology

LTC2492 Datasheet(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL