LTC2496 datasheet(18/32 Pages) LINER

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LTC2496

2496fa

Table 4. Serial Interface Timing Modes

CONFIGURATION

SCK

SOURCE

CONVERSION

CYCLE CONTROL

DATA OUTPUT

CONTROL

CONNECTION AND

WAVEFORMS

External SCK, Single Cycle

Conversion

External

⎯C⎯S and SCK

Figures 4, 5

External SCK, 3-Wire I/O

External

SCK

Figure 6

Internal SCK, Single Cycle

Conversion

Internal

⎯C⎯S↓

Figures 7, 8

Internal SCK, 3-Wire I/O,

Continuous Conversion

Internal

Continuous

Internal

Figure 9

APPLICATIONS INFORMATION

External Serial Clock, Single Cycle Operation

This timing mode uses an external serial clock to shift out

the conversion result and ⎯C⎯S to monitor and control the

state of the conversion cycle, see Figure 4.

The external serial clock mode is selected during the power-

up sequence and on each falling edge of ⎯C⎯S. In order to

enter and remain in the external SCK mode of operation,

SCK must be driven LOW both at power up and on each

⎯C⎯S falling edge. If SCK is HIGH on the falling edge of ⎯C⎯S,

the device will switch to the internal SCK mode.

The serial data output pin (SDO) is Hi-Z as long as ⎯C⎯S is

HIGH. At any time during the conversion cycle, ⎯C⎯S may be

pulled LOW in order to monitor the state of the converter.

While ⎯C⎯S is LOW, ⎯E⎯O⎯C is output to the SDO pin.

⎯E⎯O⎯C = 1 while a conversion is in progress and ⎯E⎯O⎯C = 0 if

the conversion is complete and the device is in the sleep

state. Independent of ⎯C⎯S, the device automatically enters

the sleep state once the conversion is complete; however,

in order to reduce the power, ⎯C⎯S must be HIGH.

μF

0.1

μF

2.7V TO 5.5V

Hi-Z

2496 F04

SCK

(EXTERNAL)

SDI

SDO

CONVERSION

SLEEP

DATA INPUT/OUTPUT

CONVERSION

VCC

REF+

REF–

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

1,3,4,5,6,31,32,33,39

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

LTC2496

4-WIRE

SPI INTERFACE

•

EOC

SGL

ODD

DON'T CARE

MSB

SIG

“0”

LSB

BIT 23

BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Figure 4. External Serial Clock, Single Cycle Operation

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