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LTC3445

3445fa

When VCC1 rises above 2.8V, the PowerPath’s LDO is

enabled and set to the lesser of 3V or VCC1. Once VTRACK

is 3V or higher, it controls the PowerPath’s LDO output

(VCC BATT) voltage to within 200mV of VTRACK. Note that

VTRACK needs to be less than or equal to VCC1. When

VTRACK falls below 3V, VCC1 is used to regulate the

PowerPath’s LDO (VCC BATT) to 3V. When VCC1 falls

below 2.4V, the PowerPath LDO is disconnected and

VBACKUP is connected to VCC BATT.

The PowerPath’s fault detection circuit uses an open-drain

driver (BATTFAULT) to report when the main battery is

disconnected.

Figure 5 shows the different states of the PowerPath

circuits. Typically, VBACKUP is a coin cell; however, other

types of back up power supplies may be used.

General I2C Bus/SMBus Description

I2C Bus and SMBus are reasonably similar examples of

2-wire, bidirectional, serial communications busses. Call-

ing them 2-wire is not strictly accurate, as there is an

implied third wire, which is the ground line. Large ground

drops or spikes between the grounds of different parts on

the bus can interrupt or disrupt communications, as the

signals on the two wires are both inherently referenced to

a ground which is expected to be common to all parts on

the bus. Both bus types have one data line and one clock

line which are externally pulled to a high voltage when they

are not being controlled by a device on the bus. The

devices on the bus can only pull the data and clock lines

low, which makes it simple to detect if more than one

device is trying to control the bus; eventually, a device will

release a line and it will not pull high because another

device is still holding it low. Pull-ups for the data and clock

lines are usually provided by external discrete resistors,

but external current sources can also be used. Since there

are no dedicated lines to use to tell a given device if another

device is trying to communicate with it, each device must

have a unique address to which it will respond. The first

part of any communication is to send out an address on the

bus and wait to see if another device responds to it. After

a response is detected, meaningful data can be exchanged

between the parts.

Typically, one device will control the clock line at least

most of the time and will normally be sending data to the

other parts and polling them to send data back to it, and

this device is called the master. There can certainly be

more than one master, since there is an effective protocol

to resolve bus contentions, and non-master (slave) de-

vices can also control the clock to delay rising edges and

give themselves more time to complete calculations or

communications (clock stretching). Slave devices need to

OPERATIO (refer to Figure 1)

Figure 6. Typical 2-Wire Serial I2C Waveforms

Figure 5

2.4V

2.8V

3.6V

4.2V

VCC1

VTRACK

3445 F05

VBACKUP

BATTFAULT = 1

ADDRESS

START

CONDITION

R/W

1-7

SCL

SDA

1-7

3445 F06

STOP

CONDITION

ACK

DATA

I2C OPERATION

• Simple 2-wire interface

• Multiple devices on same bus

• Idle bus must have SDA and SCL lines high

• LTC3445 is read/write

• Master controls bus

• Devices listen for unique address that precedes data

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