LTC3445 datasheet(18/24 Pages) LINER

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LTC3445

3445fa

where f = operating frequency, COUT = output capacitance

and

∆IL = ripple current in the inductor. For a fixed output

voltage, the output ripple is highest at maximum input

voltage since

∆IL increases with input voltage.

Aluminum electrolytic and dry tantalum capacitors are

both available in surface mount configurations. In the case

of tantalum, it is critical that the capacitors are surge tested

for use in switching power supplies. An excellent choice is

the AVX TPS series of surface mount tantalum. These are

specially constructed and tested for low ESR so they give

the lowest ESR for a given volume. Other capacitor types

include Sanyo POSCAP, Kemet T510 and T495 series, and

Sprague 593D and 595D series. Consult the manufacturer

for other specific recommendations.

Using Ceramic Input and Output Capacitors

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. Because the

LTC3445’s control loop does not depend on the output

capacitor’s ESR for stable operation, ceramic capacitors

can be used freely to achieve very low output ripple and

small circuit size.

However, care must be taken when ceramic capacitors are

used at the input and the output. When a ceramic capacitor

is used at the input and the power is supplied by a wall

adapter through long wires, a load step at the output can

induce ringing at the input, VCC1. At best, this ringing can

couple to the output and be mistaken as loop instability. At

worst, a sudden inrush of current through the long wires

can potentially cause a voltage spike at VCC1, large enough

to damage the part.

When choosing the input and output ceramic capacitors,

choose the X5R or X7R dielectric formulations. These

dielectrics have the best temperature and voltage charac-

teristics of all the ceramics for a given value and size.

Buck Output Voltage Programming

The LTC3445 has an internal resistor divider network tied

to the FB pin. The output voltage is controlled by a DAC

(6-bit register) whose setting is controlled by the I2C

interface. The effective DAC bit range is from 0 to 48. Note

that any DAC settings above 48 defaults to the 48 setting.

The DAC controls the VOUT range of 0.85V to 1.55V in

~15mV steps. The default value for VOUT is 1.35V and is

reset to this value whenever VCC1 comes up.

When the DAC’s value is changed, LTC3445 controls

VOUT’s slew rate via a 2-bit RATE register. The RATE

can be set to approximately 0.9mV/

µs,3.8mV/µs,7.5mV/µs

or 11.3mV/

µs. The default value for RATE is 10mV/µs and

is reset to this value whenever VCC1 comes up.

The DAC and RATE values are not lost whenever the RUN

pin is deasserted.

Once the DAC and RATE registers are programmed, a GO

bit transition is required for the buck to update. This is

accomplished by changing the GO bit (REG2[0]) from

logic low to a logic high.

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses in LTC3445 buck regulator circuits: VCC1 quiescent

current and I2R losses. The VCC1 quiescent current loss

dominates the efficiency loss at very low load currents

whereas the I2R loss dominates the efficiency loss at

medium to high load currents. In a typical efficiency plot,

the efficiency curve at very low load currents can be

misleading since the actual power lost is of no conse-

quence as illustrated in Figure 8.

1. The VCC1 quiescent current is due to two components:

the DC bias current as given in the Electrical Character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the

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